Presents scalable packed layouts and extensions to tiling/fusion/vectorization in MLIR/IREE for VLA ML code generation on Arm SVE, achieving up to 1.45x speedup over NEON and outperforming PyTorch frameworks.
InEuropean Conference on Parallel Processing (2020), Springer, pp
1 Pith paper cite this work. Polarity classification is still indexing.
1
Pith paper citing it
citation-role summary
background 1
citation-polarity summary
fields
cs.PF 1years
2026 1verdicts
CONDITIONAL 1roles
background 1polarities
background 1representative citing papers
citing papers explorer
-
Scalable Packed Layouts for Vector-Length-Agnostic ML Code Generation
Presents scalable packed layouts and extensions to tiling/fusion/vectorization in MLIR/IREE for VLA ML code generation on Arm SVE, achieving up to 1.45x speedup over NEON and outperforming PyTorch frameworks.