ChatSVA achieves 96.12% functional pass rate and 82.5% coverage in SVA generation on 24 RTL designs, delivering 33 percentage point gains and 11x better coverage than prior state-of-the-art.
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VeriPilot raises GPT-4o Verilog repair success from 54.3% to 85.71% on the CVDP benchmark by using golden-model semantic alignment and CDFG-based signal tracing.
SVA Generator improves semantic correctness of LLM-generated SystemVerilog Assertions by 22.7 percentage points on average for deeper properties using AST-grounded constraint injection and depth-stratified formal equivalence checking.
citing papers explorer
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ChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMs
ChatSVA achieves 96.12% functional pass rate and 82.5% coverage in SVA generation on 24 RTL designs, delivering 33 percentage point gains and 11x better coverage than prior state-of-the-art.
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VeriPilot: An LLM-Powered Verilog Debugging Framework
VeriPilot raises GPT-4o Verilog repair success from 54.3% to 85.71% on the CVDP benchmark by using golden-model semantic alignment and CDFG-based signal tracing.
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Automated SVA Generation with LLMs
SVA Generator improves semantic correctness of LLM-generated SystemVerilog Assertions by 22.7 percentage points on average for deeper properties using AST-grounded constraint injection and depth-stratified formal equivalence checking.