Crosstalk between parallel entangling gates in a 2D trapped-ion chip requires a distance-5 surface code, and with optimized parallelism logical error rates below 10^-10 are reachable with hundreds to thousands of ions.
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Performance Analysis for Crosstalk Errors between Parallel Entangling Gates in Trapped Ion Quantum Error Correction
Crosstalk between parallel entangling gates in a 2D trapped-ion chip requires a distance-5 surface code, and with optimized parallelism logical error rates below 10^-10 are reachable with hundreds to thousands of ions.