A sparse-friendly systolic array reuses a small number of MAC units across a larger virtual grid to exploit unstructured weight sparsity, with simulated area and power efficiency gains in a commercial 16-nm process.
Exploiting neural-network statistics for low-power DNN inference,
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VUSA: Virtually Upscaled Systolic Array Architecture to Exploit Unstructured Sparsity in AI Acceleration
A sparse-friendly systolic array reuses a small number of MAC units across a larger virtual grid to exploit unstructured weight sparsity, with simulated area and power efficiency gains in a commercial 16-nm process.