ref [34] · 2506.19964 · notice #10382 · dispute
Raw extraction · citation context
: Scaling out ising machines using a multi- chip architecture for simulated bifurcation. Nature Electronics4(3), 208-217 (2021) https://doi.org/10.1038/s41928-021-00546-4 [34] Wang, H., Liu, Z., Xie, Z., Li, L., Miao, Z., Cui, W., Pan, Y.: Parallel ising annealer via gradient-based hamiltonian monte carlo. Quantum Machine Intelligence7(1), 6 (2025) https://doi.org/10.1007/s42484-024-00231-7 [35] Yamamoto, K., Kawamura, K., Ando, K., Mertig, N., Takemoto, T., Yamaoka, M., Teramoto, H., Sakai, A., Takamaeda-Yamazaki, S., Motomura, M.: Statica: A 512-spin 0.25m-weight annealing processor with an all-spin-updates-at-once architecture for combinatorial optimization with complete spin-spin interactions. IEEE Journal of Solid-State Circuits56(1), 165-178 (2021) https://doi.
Parser render (TeX stripped for reading; raw above is the evidence)
: Scaling out ising machines using a multi- chip architecture for simulated bifurcation. Nature Electronics4(3), 208-217 (2021) https://doi.org/10.1038/s41928-021-00546-4 [34] Wang, H., Liu, Z., Xie, Z., Li, L., Miao, Z., Cui, W., Pan, Y.: Parallel ising annealer via gradient-based hamiltonian monte carlo. Quantum Machine Intelligence7(1), 6 (2025) https://doi.org/10.1007/s42484-024-00231-7 [35] Yamamoto, K., Kawamura, K., Ando, K., Mertig, N., Takemoto, T., Yamaoka, M., Teramoto, H., Sakai, A., Takamaeda-Yamazaki, S., Motomura, M.: Statica: A 512-spin 0.25m-weight annealing processor with an all-spin-updates-at-once architecture for combinatorial optimization with complete spin-spin interactions. IEEE Journal of Solid-State Circuits56(1), 165-178 (2021) https://doi