A Novel Hierarchical Circuit LUT Model for SOI Technology for Rapid Prototyping

Akanksha Yadav; Ganesh R. Gore; Krishnan S. Rengarajan; Mahesh B. Patil; Maryam Shojaei Baghini; Sitansusekhar Roymohapatra; Subhramanian S. Iyer

arxiv: 1903.11264 · v2 · pith:TWARJ7BMnew · submitted 2019-03-27 · 💻 cs.AR

A Novel Hierarchical Circuit LUT Model for SOI Technology for Rapid Prototyping

Sitansusekhar Roymohapatra , Ganesh R. Gore , Akanksha Yadav , Mahesh B. Patil , Krishnan S. Rengarajan , Subhramanian S. Iyer , Maryam Shojaei Baghini This is my paper

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A Novel Hierarchical Circuit LUT Model for SOI Technology for Rapid Prototyping

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