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Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm

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arxiv 2109.03024 v1 pith:CASWQFPT submitted 2021-08-01 cs.AR

Sung Kim , Morteza Fayazi , Alhad Daftardar , Kuan-Yu Chen , Jielun Tan , Subhankar Pal , Tutu Ajayi , Yan Xiong
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Trevor Mudge Chaitali Chakrabarti David Blaauw Ronald Dreslinski Hun-Seok Kim
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classification cs.AR
keywords versaaccesscharacteristicscorescortex-m4fdatahierarchysystolic
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We present Versa, an energy-efficient processor with 36 systolic ARM Cortex-M4F cores and a runtime-reconfigurable memory hierarchy. Versa exploits algorithm-specific characteristics in order to optimize bandwidth, access latency, and data reuse. Measured on a set of kernels with diverse data access, control, and synchronization characteristics, reconfiguration between different Versa modes yields median energy-efficiency improvements of 11.6x and 37.2x over mobile CPU and GPU baselines, respectively.

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