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The Championship Simulator: Architectural Simulation for Education and Competition

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arxiv 2210.14324 v1 pith:JPUUXW3O submitted 2022-10-25 cs.AR

classification cs.AR
keywords complexityfieldchampsimcoreincreasemicroarchitecturearchitecturecompetition
verification ladder T0 review T1 audit T2 compute T3 formal
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Recent years have seen a dramatic increase in the microarchitectural complexity of processors. This increase in complexity presents a twofold challenge for the field of computer architecture. First, no individual architect can fully comprehend the complexity of the entire microarchitecture of the core. This leads to increasingly specialized architects, who treat parts of the core outside their particular expertise as black boxes. Second, with increasing complexity, the field becomes decreasingly accessible to new students of the field. When learning core microarchitecture, new students must first learn the big picture of how the system works in order to understand how the pieces all fit together. The tools used to study microarchitecture experience a similar struggle. As with the microarchitectures they simulate, an increase in complexity reduces accessibility to new users. In this work, we present ChampSim. ChampSim uses a modular design and configurable structure to achieve a low barrier to entry into the field of microarchitecural simulation. ChampSim has shown itself to be useful in multiple areas of research, competition, and education. In this way, we seek to promote access and inclusion despite the increasing complexity of the field of computer architecture.

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Cited by 13 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score.

  1. Beyond Static Policies: Dynamic Selection Among Modern Microarchitectural Policies

    cs.AR 2026-08 conditional novelty 7.0 of 10

    A binary runtime choice between two L1D prefetchers recovers most of the performance left by any fixed policy, with a small decision tree or bandit rule as the selector.

  2. Themis: Software-Defined Hardware Prefetching

    cs.AR 2026-07 conditional novelty 7.0 of 10

    Page-granular, profile-computed prefetch-disable hints stored in page-table entries reduce useless hardware prefetches by ~40% and improve IPC by 0.2–13.8% across seven prefetchers on datacenter traces.

  3. ArchEval: Measuring AI Agents as Computer Architects

    cs.AR 2026-07 conditional novelty 7.0 of 10

    LLM agents beat architecture baselines with full simulator harnesses, but only one configuration stays above baseline without feedback, and performance modeling remains weak.

  4. CHIA: An open-source framework for principled, agentic AI-driven hardware/software co-design research

    cs.AR 2026-06 unverdicted novelty 7.0 of 10

    CHIA introduces a framework for building and deploying agentic AI co-design flows as CHIA loops with tool nodes, reliability mechanisms, and five case-study demonstrations.

  5. CHIA: An open-source framework for principled, agentic AI-driven hardware/software co-design research

    cs.AR 2026-06 unverdicted novelty 7.0 of 10

    CHIA is an open-source framework for agentic AI-driven hardware/software co-design using CHIA loops as directed cyclic graphs, a tool library, and features for reliable experimentation, shown via five case studies.

  6. AgentDSE: Reasoning-Augmented Architectural Design Space Exploration

    cs.AR 2026-06 unverdicted novelty 7.0 of 10

    AgentDSE uses an LLM agent in a simulator-in-the-loop setup to achieve competitive or superior architectural designs with up to 100x fewer evaluations than traditional black-box optimization methods.

  7. Enhancing Instruction Prefetching via Cache and TLB Management

    cs.AR 2026-05 unverdicted novelty 7.0 of 10

    IP-CaT jointly optimizes TLB and cache management for L1I prefetching via a translation prefetch buffer and trimodal replacement policy, yielding 8.7% geomean speedup over EPI across 105 server workloads.

  8. PIMID: A Full-System Simulator with Intricacy and Diversity for Processing-in-Memory

    cs.AR 2026-07 conditional novelty 6.5 of 10

    PIMID unifies dual-execution-model, multi-technology, multi-placement PIM simulation and finds technology, PE scaling, and message-passing collectives dominate end-to-end time and energy.

  9. Microflow: Microarchitectural Causal Observability for Deep Cross-Layer Analysis and Optimization

    cs.AR 2026-07 conditional novelty 6.0 of 10

    Microflow builds a typed causal graph from simulator traces so that stalls can be traced across software, pipeline, and resource layers, exposing root causes such as a RAS corruption cascade in leela and cross-loop co...

  10. CHIA: An open-source framework for principled, agentic AI-driven hardware/software co-design research

    cs.AR 2026-06 conditional novelty 6.0 of 10

    CHIA is a distributed graph-based framework for composing, deploying, and verifying agentic AI hardware/software co-design flows, demonstrated on RTL, simulation, and compiler tasks.

  11. Agentic Architect: An Agentic AI Framework for Architecture Design Exploration and Optimization

    cs.AI 2026-04 accept novelty 6.0 of 10

    An LLM-driven agentic system evolves microarchitectural policies for cache replacement, data prefetching, and branch prediction, producing designs that match or exceed prior state-of-the-art in IPC on standard benchmarks.

  12. Beyond Static Policies: Exploring Dynamic Policy Selection for Single-Thread Performance Optimization

    cs.AR 2026-05 conditional novelty 5.0 of 10

    Dynamic selection between two cache/prefetch policies reduces mean IPC loss from 1.54% to 0.11% versus an oracle across 490 workload phases.

  13. Vulcan: Instance-specialized, Verifiable Systems Heuristics Through LLM-driven Search

    cs.OS 2025-12 reject novelty 5.0 of 10

    Vulcan finds instance-specific cache and memory-tiering heuristics via LLM-driven evolutionary search, but its evaluation overlaps training traces with test traces and the abstract overstates the body's results.

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