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arxiv: 2501.09020 · v3 · submitted 2025-01-15 · 💻 cs.AR

Octopus: Enhancing CXL Memory Pods via Sparse Topology

Yuhong Zhong , Fiodar Kazhamiaka , Pantea Zardoshti , Shuwei Teng , Rodrigo Fonseca , Mark D. Hill , Daniel S. Berger This is my paper

Pith reviewed 2026-05-23 05:10 UTC · model grok-4.3

classification 💻 cs.AR
keywords CXLmemory poolingsparse topologyisland groupingRPC latencyserver cost savingsCXL podsinterconnect design
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The pith

Octopus uses sparse CXL connections and server islands to scale memory pods without switches while cutting RPC latency and costs.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

Existing CXL memory pod designs stay small or rely on expensive switches because they assume every server must connect to every pooling device. Octopus breaks this by building a sparse topology where each low-port pooling device links only to a chosen subset of servers. Servers are grouped into islands so that communication stays fast inside each island while overlap between islands supports efficient memory sharing across the pod. The design respects physical limits like 1.5-meter copper cables and scales to 96 servers. Hardware measurements show RPCs run 3.2 times faster than in-rack RDMA and 2.4 times faster than CXL switches, and simulations report 3 to 5.4 percent net server cost savings.

Core claim

Octopus constructs a sparse CXL topology in which each pooling device connects to a carefully chosen subset of servers grouped into islands; this arrangement delivers low-latency intra-island communication, sufficient inter-island overlap for pooling, and scalability to large pods without switches while staying inside 1.5 m cable constraints.

What carries the argument

Island grouping that creates low-latency clusters while allowing controlled overlap between clusters for memory pooling.

If this is right

  • RPCs complete 3.2 times faster than in-rack RDMA on the hardware prototype.
  • RPCs complete 2.4 times faster than through CXL switches on the hardware prototype.
  • Simulated 96-server pods deliver 3 to 5.4 percent net server cost savings.
  • CXL-switch designs produce a net cost increase in the same simulations.
  • The topology respects 1.5 m copper cable limits while scaling to 96 servers.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same sparse-island pattern could be tested on other disaggregated interconnects such as PCIe or NVLink to see if similar latency and cost gains appear.
  • Dynamic adjustment of island boundaries at runtime might further improve overlap for changing workload patterns.
  • Reducing reliance on switches could lower overall rack power draw even if the paper does not measure power directly.
  • Standards bodies might consider specifying lower port counts on future CXL devices if sparse topologies prove reliable at scale.

Load-bearing premise

A carefully chosen sparse subset of connections per pooling device combined with island grouping can satisfy low-latency intra-island communication, sufficient inter-island pooling overlap, and physical cable length limits without hidden performance or scalability penalties.

What would settle it

Running the three-server hardware prototype at larger scale, such as 16 servers, and checking whether RPC latency remains 3.2 times faster than RDMA and net cost savings stay positive under measured device characteristics and 1.5 m cables.

Figures

Figures reproduced from arXiv: 2501.09020 by Daniel S. Berger, Fiodar Kazhamiaka, Mark D. Hill, Pantea Zardoshti, Rodrigo Fonseca, Shuwei Teng, Yuhong Zhong.

Figure 2
Figure 2. Figure 2: Multi-ported device with two CXL ports. Each port offers x8 CXL lanes. to one PD (minimally-connected Octopus) or multiple PDs (redundantly-connected Octopus). This paper makes the following technical contributions. • First paper to question the assumption that pods must fully-connect hosts and pooling devices • Propose Octopus pod designs with bounded connec￾tions and provide algorithmic constructions for… view at source ↗
Figure 1
Figure 1. Figure 1: Conventional CXL pod designs assume that all 16 hosts (𝐻0 to 𝐻15) connect to all pooling devices, which re￾quires a still-expensive 16-ported device. Octopus introduces minimally-connected pod designs based on near-commodity 4-port pooling devices, which cuts pooling device cost in half. than the overall pod size. Similarly, we find that communica￾tion largely requires pair-wise memory sharing. We propose … view at source ↗
Figure 3
Figure 3. Figure 3: Larger CXL pods lead to higher DRAM savings. Besides PDs, another approach to build a pool is a switch. Switches offer multiple CXL ports and can forward CXL packets between them. An example is the XC50256 CXL switch offered by XConn [110]. A CXL pod comprises multiple hosts using multiple PDs and/or switches. In principle, hosts can concurrently access the memory behind a PD or behind a switch. However, w… view at source ↗
Figure 4
Figure 4. Figure 4: Die area estimates for PDs with different numbers of CXL ports and DDR5 channels. Note that for visual sim￾plicity we show the logic and network-on-chip (NOC) area as a single block. PD Size 𝑁 = 2 𝑁 = 4 𝑁 = 8 𝑁 = 16 DDR5 channels 2 4 8 12 References [40, 54, 77] [38] [81] Overall die area 14 𝑚𝑚2 30 𝑚𝑚2 69 𝑚𝑚2 181 𝑚𝑚2 Dead silicon 0 𝑚𝑚2 2 𝑚𝑚2 12 𝑚𝑚2 77 𝑚𝑚2 Wafer cost 70% 80% 100% 150% Estimated cost𝑎 $260 $… view at source ↗
Figure 5
Figure 5. Figure 5: A 3-rack Octopus configuration. 5.2 Physical Layout The physical layout of an Octopus topology is largely driven by CXL cable lengths and cable routing. CXL 2.0 (PCIe5) systems are typically constrained by insertion loss, which admits a simplified analysis. Under a 36 dB insertion-loss bud￾get at 16 GHz, we allocate 8 dB for pad-to-pin (root complex) and 10 dB for the CXL pooling device. We conservatively … view at source ↗
Figure 6
Figure 6. Figure 6: Host software view in fully-connected and Octopus pods. H1 P1 P2... H2 H3 PX+1 H1 P1 P2... H2 H3 PX+1 [PITH_FULL_IMAGE:figures/full_fig_p007_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: Pair-wise message passing and shuffle 6.1 Software CXL Pod API In a fully-connected topology, memory is interleaved across CXL PDs by default. Specifically, CXL specifies hardware interleaving at 256 Byte granularity across CXL devices con￾nected to a CPU socket [20].2 Figure 6a shows the host mem￾ory map in a typical fully-connected topology. Octopus makes individual CXL ports visible to the Operat￾ing Sy… view at source ↗
Figure 9
Figure 9. Figure 9: Fully-connected CXL pod topologies define a Pareto frontier where cost rises super-linearly with CXL pod size. For medium to large pod sizes, Octopus can achieve much larger pod sizes at equal or lower cost. D            [PITH_FULL_IMAGE:figures/full_fig_p009_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: Additional memory required by Octopus relative to a FC design with the same host count for three production workloads. Note that a need for 5% more memory comparable favorably to enabling 4.5× larger host counts ( [PITH_FULL_IMAGE:figures/full_fig_p009_10.png] view at source ↗
Figure 12
Figure 12. Figure 12: Distribution of RPC round-trip latency for small and large messages. CXL’s latency is 3.3× and 1.5× lower than RDMA, and 10× lower than user-space networking. RPC services see median request sizes under 1500 Bytes with resonses under 315 Bytes [94]. At Meta, almost all KVS re￾quest sizes fit into 128 Bytes and response sizes are typically around 1-10kB [15]. For small messages, a minimally-connected Octop… view at source ↗
Figure 13
Figure 13. Figure 13: Minimally-connected Octopus topologies for the common case of 𝑋 = 8 host ports. (a) visualizes design #2 in [PITH_FULL_IMAGE:figures/full_fig_p017_13.png] view at source ↗
Figure 15
Figure 15. Figure 15: Redundantly-connected Octopus topology for 𝑁 = 4-ported PDs and the common case of 𝑋 = 8 host ports (design #6 in [PITH_FULL_IMAGE:figures/full_fig_p018_15.png] view at source ↗
Figure 14
Figure 14. Figure 14: Minimally-connected Octopus topology for 𝑁 = 2-ported PDs and the common case of 𝑋 = 8 host ports (design #1 in [PITH_FULL_IMAGE:figures/full_fig_p018_14.png] view at source ↗
Figure 16
Figure 16. Figure 16: Assuming that wafers cost half as much as in [PITH_FULL_IMAGE:figures/full_fig_p021_16.png] view at source ↗
Figure 17
Figure 17. Figure 17: Assuming that wafers cost twice as much as in [PITH_FULL_IMAGE:figures/full_fig_p021_17.png] view at source ↗
read the original abstract

The Compute Express Link (CXL) interconnect enables compute "pods" that pool memory across servers to reduce cost and improve efficiency. These pods also facilitate pairwise communication whose needs conflict with pooling. Importantly, existing pod designs are small or require indirection through expensive switches. These conventional designs implicitly assume that pods must fully connect all servers to all CXL pooling devices. This paper breaks with this conventional wisdom by introducing Octopus pods. Octopus directly connects servers to low-port-count CXL pooling devices (e.g., 4 ports) yet scales to large pods without switches by constructing a sparse CXL topology in which each pooling device connects to a carefully chosen subset of servers. Octopus explicitly balances "overlap", where two servers connect to the same pooling device: overlap reduces pooling efficiency but enables low-latency communication. Octopus resolves this tension by grouping servers into "islands" with low-latency intra-island communication and interconnecting islands to favor pooling. We build a three-server CXL pod prototype and simulate scaled pods with 96 servers under measured device characteristics and physical constraints (1.5 m copper cables). On hardware, Octopus RPCs are 3.2x faster than in-rack RDMA and 2.4x faster than CXL switches. In simulation, Octopus achieves net server cost savings of 3-5.4% whereas CXL switches result in a net cost increase.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The paper claims that conventional CXL memory pods require full connectivity or expensive switches, but Octopus enables scalable pods by using low-port-count pooling devices in a sparse topology: servers are grouped into islands for low-latency intra-island communication while islands are interconnected to maintain sufficient pooling overlap, all subject to 1.5 m cable limits. A 3-server hardware prototype demonstrates 3.2x faster RPCs than in-rack RDMA and 2.4x faster than CXL switches; 96-server simulations under measured device traits report 3-5.4% net server cost savings (versus net increases with switches).

Significance. If the central claims hold, the work could meaningfully reduce the cost and complexity of large CXL pods by eliminating switches while preserving both pooling efficiency and low-latency pairwise communication. Strengths include the hardware prototype driven by real device characteristics and physical cable constraints, plus the explicit framing of the overlap-versus-pooling tension. The island-based sparse construction is a concrete alternative to the full-connectivity assumption in prior designs.

major comments (2)
  1. [§4] §4 (Hardware Prototype): The three-server prototype permits near-full connectivity within the 1.5 m cable limit, so the measured 3.2x RPC speedup does not exercise the island-grouping or sparse-subset tension that the 96-server simulation claims to resolve; this leaves the simulation cost savings dependent on an unvalidated extrapolation.
  2. [§5] §5 (Simulation Results): The algorithm or procedure used to select the sparse per-device subsets and to define island boundaries is not described with sufficient detail (no pseudocode, parameters, or validation against cable and overlap constraints), so the reported 3-5.4% savings cannot be independently checked for robustness under the stated physical limits.
minor comments (2)
  1. [Abstract] Abstract: omits any mention of how sparse subsets or island boundaries are chosen, which is load-bearing for the claimed benefits.
  2. [§3] Figure captions and §3 notation for overlap and pooling metrics could be made more precise to aid readability.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for their thoughtful and constructive review. We address each major comment below, indicating where revisions will be made to the manuscript.

read point-by-point responses

  1. Referee: [§4] §4 (Hardware Prototype): The three-server prototype permits near-full connectivity within the 1.5 m cable limit, so the measured 3.2x RPC speedup does not exercise the island-grouping or sparse-subset tension that the 96-server simulation claims to resolve; this leaves the simulation cost savings dependent on an unvalidated extrapolation.

    Authors: We agree with the referee that the three-server prototype, given its small scale, permits near-full connectivity within the cable length limit and therefore does not fully exercise the sparse topology or island-grouping mechanism central to the 96-server simulation. The prototype primarily serves to validate the performance of direct CXL connections using real hardware and measured device characteristics under physical constraints. The simulation then applies these traits to larger sparse configurations. This represents a genuine limitation in hardware validation of the scaling claims. In the revised manuscript, we will update §4 to clearly distinguish the prototype's contributions from the simulation, explicitly note the extrapolation involved, and discuss potential avenues for further validation. We will also add a brief sensitivity analysis in the simulation section if space permits. revision: partial

  2. Referee: [§5] §5 (Simulation Results): The algorithm or procedure used to select the sparse per-device subsets and to define island boundaries is not described with sufficient detail (no pseudocode, parameters, or validation against cable and overlap constraints), so the reported 3-5.4% savings cannot be independently checked for robustness under the stated physical limits.

    Authors: The referee is correct that the current manuscript lacks detailed description of the algorithm for selecting sparse subsets and defining island boundaries. No pseudocode or explicit parameters are provided, which hinders reproducibility and independent verification of the results under the cable and overlap constraints. We will revise the paper by adding a new subsection in §5 (or an appendix) that includes: (1) pseudocode for the island construction and subset selection procedure, (2) all relevant parameters and thresholds used (e.g., overlap targets, cable length enforcement), and (3) validation checks ensuring the generated topologies respect the 1.5 m limit and maintain required pooling overlap. This will allow readers to reproduce and assess the robustness of the 3-5.4% cost savings. revision: yes

Circularity Check

0 steps flagged

No significant circularity; empirical results from hardware and external measurements

full rationale

The paper reports latency and cost numbers directly from a 3-server hardware prototype and from simulations driven by measured device characteristics plus physical cable constraints (1.5 m). No equations, fitted parameters, or topology-construction procedure are shown to be self-definitional or to rename a prediction as a result. The central design choice (sparse island-based topology) is presented as an engineering tradeoff rather than a derived theorem, and quantitative claims do not reduce to the inputs by construction. This is the normal case of a measurement-driven systems paper.

Axiom & Free-Parameter Ledger

0 free parameters · 2 axioms · 0 invented entities

The design rests on domain assumptions about CXL device port counts and physical cable constraints rather than new fitted parameters or invented entities.

axioms (2)
  • domain assumption CXL pooling devices have low port counts (e.g., 4 ports)
    Explicitly used as the starting point for the sparse topology construction.
  • domain assumption Physical cable length is limited to 1.5 m copper
    Invoked as a constraint in the 96-server simulations.

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