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REVIEW 3 major objections 7 minor 98 references

TEGRA: A Flexible & Scalable NextGen Mobile Core

T0 review · 3 major / 7 minor · reviewed 2026-08-04 · deepseek-v4-flash

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Pith's one-line read TEGRA shows a 3GPP service-based mobile core can match a consolidated monolithic core's latency while preserving microservice flexibility.

desk verdict A well-engineered SBA 5G core with real speedups over Aether/free5GC/Open5GS, but the headline 'matches CoreKube' claim rests on an invented baseline that should not survive as stated. read the letter →

arxiv 2509.07410 v1 pith:U3RHQ7BD submitted 2025-09-09 cs.NI

Bilal Saleem , Omar Basit , Jiayi Meng , Iftekhar Alam , Ajay Thakur , Christian Maciocco , Muhammad Shahbaz , Y. Charlie Hu
show 1 more author
Larry Peterson
This is my paper · ORCID
classification cs.NI
keywords 5Gcoreservice-basedarchitecturemobilemicroservicescontrolplaneautoscalingresilienceloadbalancing
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper asks whether a service-based 5G mobile core must sacrifice scalability and performance to stay flexible. It answers no, by proposing TEGRA, a 3GPP-compliant core that keeps per-user state in service instances, routes both upstream and downstream control messages to the same instance, and shares load and state information through a distributed publish-subscribe mechanism. In experiments on a three-server edge cloud, TEGRA processes registration, PDU session, and service-request events up to 1.74x, 1.5x, and 1.75x faster than Aether at 256 UEs, and roughly matches the projected performance of the consolidated CoreKube baseline. The paper also claims TEGRA needs orders of magnitude fewer lines of code to add a new service or event, because deploying a new feature can be a single-line configuration change. The broader claim is that the perceived tradeoff between SBA flexibility and control-plane performance is not inherent.

What carries the argument

The design rests on four microservice patterns: Gateway (separate SCTP and PFCP termination services that proxy into the core), Long-Running (stateful services like AMF, SMF, NRF that keep a soft per-UE cache), Ephemeral (stateless services like UDM, PCF that transform messages without local state), and Storage (persistent databases for UE and service state). These are carried by two mechanisms: UELB, a client-side load balancer that pins each UE to one service instance based on the UE identifier, and DRSM, a distributed publish-subscribe state-sharing service that keeps instances aware of each other's load, instance count, and allocated ID/IP blocks. The soft-state caching is what reduces s

What would settle it

On the same three-server edge cloud, implement the missing Service Request, PDU session, and UPF support in CoreKube and measure end-to-end control-plane latency at 256 UEs for Registration, PDU establishment, and Service Request; if the completed CoreKube's actual latencies are materially below TEGRA's, the paper's central parity claim fails.

Watch

Extended reading notes

Core claim

TEGRA is a high-performance, flexible, scalable, and resilient SBA-based 5G core that avoids reverting to NFV-style consolidation. Its core discovery is that the mobile core's position at the network edge, handling bidirectional asynchronous control events from both UEs and the Internet, allows cloud-native techniques to be re-designed: per-UE soft state cached inside service instances with asynchronous persistence to storage, UE-based sticky load balancing so both directions of a UE's traffic hit the same instance, and a distributed resource-sharing mechanism (DRSM) that shares load and allocation state without a central scheduler. The paper reports end-to-end control-plane latency improvem

Load-bearing premise

The claim that TEGRA matches CoreKube's performance rests on a projected ~CoreKube baseline built by estimating missing lines of code and scaling measured latency on a 2.2 GHz CPU; if that projection is inaccurate, the parity claim is unsupported.

Editorial extensions

If this is right

  • If TEGRA's central claim holds, operators can horizontally autoscale individual control-plane services like AMF and SMF without losing consistency, because UE-sticky routing keeps bidirectional messages on the same instance.
  • The soft-state approach implies steady-state control-plane latency can be close to stateful in-memory processing, while failure recovery still works by pulling the latest committed state from storage, so resilience does not have to come from sacrificing performance.
  • Adding a new service or event in TEGRA reduces to a single-line configuration change plus CI/CD deployment, versus about 1,700 lines and full recompilation in a consolidated core, which would sharply lower the cost of introducing new 5G features.
  • The paper's results suggest that consolidation-based cores such as CoreKube are not the only way to meet latency targets; a disaggregated SBA core can stay within control-plane latency budgets at hundreds of UEs and in real traces at tens of thousands of UEs.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The headline parity with CoreKube is not a direct measurement: the paper constructs a projected ~CoreKube baseline by estimating missing lines of code and scaling measured latency on a 2.2 GHz CPU, so actual parity with a completed CoreKube remains to be demonstrated.
  • The four design patterns and UE-sticky routing could generalize beyond cellular cores to other stateful edge services that receive asynchronous events from both clients and the network, such as IoT gateways or real-time session brokers.
  • Because the evaluation uses one operator's week-long control-plane trace and a custom emulator, the scalability claims are tied to that workload; testing with other operators' traces and with higher UE churn would show how much of the speedup is workload-specific.
  • TEGRA's microservice decomposition may make hardware acceleration easier: the authors point toward offloading hot services onto SmartNICs, a direction not evaluated in this paper but a natural next test.
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Signed reviews

No signed human review yet.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 7 minor

Summary. The paper argues that service-based architecture (SBA) mobile cores need not sacrifice flexibility for performance and scalability. It presents TEGRA, a Go-based SBA 5G core built by modifying Aether modules and adding gateway microservices, UE-based sticky load balancing, soft-state per-UE caching, a distributed publish/subscribe state-sharing mechanism (DRSM), and horizontal autoscaling. The evaluation on a three-server Proxmox/Kubernetes edge cloud compares TEGRA with Aether, free5GC, Open5GS, Magma, and CoreKube across Registration, PDU Session Establishment, and Service Request, using both synthetic and operator-derived real traces. The paper claims TEGRA is 20x/11x/1.75x faster than free5GC/Open5GS/Aether, matches the state-of-the-art CoreKube while retaining flexibility, and requires orders of magnitude fewer lines of code to extend.

Significance. If the central claims hold, the paper would provide a valuable counterexample to the prevailing assumption that disaggregated SBA cores must trade flexibility for latency. The evaluation is extensive: it includes multiple baselines, three control-plane events, scaling from 32 to 256 UEs, real traces, autoscaling microbenchmarks, state-cache ablation, and failure injection. The design patterns and the soft-state/sticky-load-balancing combination are concrete and plausibly generalizable. However, the headline claim that TEGRA 'matches CoreKube' rests on the authors' constructed ~CoreKube baseline rather than on a measured complete CoreKube implementation. That projection is not reproducible from the information given, and it is load-bearing for the paper's main 'no tradeoff' thesis. The other contributions remain credible, but the parity result needs either rigorous justification or removal from the central claims.

major comments (3)
  1. [§6.1.2, Figure 7, Abstract] The claim that TEGRA 'matches CoreKube' is supported only by the authors' ~CoreKube construction. Section 6.1.2 estimates missing CoreKube functionality as 67%, 71%, and 733% additional LoCs based on Open5GS, and states that the authors 'project the associated runtime overhead by scaling CoreKube's measured latency ... using a 2.2 GHz CPU.' No formula or empirical relationship connects LoC percentages to latency, and for Service Request CoreKube has no measured latency to scale. The ~CoreKube bars in Figure 7 are therefore non-reproducible. Because the Abstract and Section 6.2 use 'matches CoreKube' as evidence that flexibility does not cost performance, this is a load-bearing issue. Please either present raw CoreKube as a separate measured baseline and remove/qualify the parity claim, or provide a validated overhead model (e.g., per-function profiling) with explicit assumptions, sensiti
  2. [§6.1.3, Table 1] Table 1 labels TEGRA as 'fully 3GPP-compliant' and 'operational,' but the evaluation exercises only Registration, PDU Session Establishment, and Service Request, all via the custom gNBSimRT emulator. No conformance or interoperability tests are reported for other mandatory 3GPP procedures, such as handover, deregistration, AN release, or paging under load. The compliance claim is stronger than the presented evidence. Either add conformance evidence from a recognized test suite or narrow the claim to 'supports the evaluated procedures in a 3GPP-compliant manner.'
  3. [§6.2, Abstract] The abstract's headline '20x, 11x, and 1.75x faster than free5GC, Open5GS, and Aether' is not reconciled with Section 6.2, which explicitly reports only 'up to 1.74x speedup for Registration, 1.5x for PDU session establishment, and 1.75x for Service Request at 256 UEs compared to Aether.' The 20x and 11x numbers presumably come from comparisons with free5GC and Open5GS, but the body does not derive them. Please state the event, UE count, and baseline for each number, and ensure the abstract's claims match the presented data.
minor comments (7)
  1. [§6.2] Typo: 'looses' should be 'loses.'
  2. [§4.1.2] Typo: 'central schedular' should be 'central scheduler.'
  3. [Abstract] Formatting: 'TEGRAoptimizes performance' lacks a space; similar spacing issues appear elsewhere.
  4. [Figure 7] The figure is hard to parse from the text: panel labels, baseline indication, and the distinction between measured and projected bars should be stated in the caption. It would help to include absolute latencies and confidence intervals, not only speedups.
  5. [§6.3.5] The sentence 'Adding a new service (i.e., NRF)' is confusing because TEGRA already includes NRF. Clarify whether the experiment is adding a new NRF instance or a different service, and how the single-line config change is counted.
  6. [§2, §6.1.2] CoreKube's missing functionality is described slightly differently in the footnote (downstream PFCP support) and in §6.1.2 (SR and UPF support). Please harmonize the descriptions.
  7. [§6.1.1] gNBSimRT is built for this paper but no artifact release is mentioned. Please state whether the emulator and trace will be made available, since this affects reproducibility of the evaluation.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: TEGRA's speedups are measured against external baselines; the ~CoreKube projection is an unverified model but not a circular reduction.

full rationale

The paper's central claim is an empirical one: TEGRA, built by modifying Aether, is measured against Aether, free5GC, Open5GS, Magma, and CoreKube using the gNBSimRT emulator and a real trace. No parameter is fitted to TEGRA's own latency numbers, and no equation defines TEGRA's performance in terms of the baseline results. The only author-supplied inputs are the workload generator and trace (Sec. 6.1.1; ref [64]); these are not used to derive the speedups, so they do not make the result circular. The most arguable concern is Section 6.1.2, where the authors explicitly state CoreKube is incomplete and construct an augmented '~CoreKube' baseline by scaling CoreKube's measured latency with estimated LoC percentages (67%, 71%, 733%). This is a limitation: the paper itself notes 'we project the associated runtime overhead,' and no formula connects LoC percentages to latency, especially for SR where CoreKube has no measured latency. But this is a reproducibility/correctness weakness of the parity claim, not a circularity: TEGRA's measured improvements do not reduce by construction to the ~CoreKube estimate, and the main comparisons to Aether/free5GC/Open5GS are external and independent.

Assumptions & free parameters 1 free parameters · 3 assumptions · 0 invented entities

No analytic derivation with fitted constants is used. The only modeled quantity is the projected CoreKube overhead. Remaining assumptions concern workload representativeness and fairness of the comparison environment.

free parameters (1)
  • CoreKube completion overhead model = 67% (REG), 71% (PDU), 733% (SR) additional LoCs; latency scaled by 2.2 GHz CPU
    Used to construct the ~CoreKube baseline. It is a modeling choice by the authors, not a measurement from a complete working CoreKube implementation, and it directly affects the parity claim.
assumptions (3)
  • domain assumption gNBSimRT and the single-operator trace [64] faithfully represent real 5G control-plane workloads
    All end-to-end latency claims depend on this emulator and the week-long trace. The trace comes from author-affiliated prior work and may not generalize to other operators or deployment scales.
  • ad hoc to paper Open5GS implementations provide a valid estimate of missing CoreKube functionality and runtime overhead
    Section 6.1.2 builds ~CoreKube from Open5GS LoC estimates and CPU clock scaling. The parity claim against CoreKube rests on this assumption.
  • domain assumption Equal CPU allocation across cores under test is a fair comparison basis
    TEGRA adds gateway and storage components while Aether, free5GC, Open5GS, Magma, and CoreKube use the same 50-core workload allocation. Any imbalance in resource partitioning could bias the measured speedups.

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Cite this review

Pith. "Pith review of TEGRA: A Flexible & Scalable NextGen Mobile Core." pith.science (2026). https://pith.science/paper/U3RHQ7BD

@misc{pith2026250907410,
  author       = {Pith},
  title        = {Pith review of: TEGRA: A Flexible & Scalable NextGen Mobile Core},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/U3RHQ7BD}},
  note         = {Machine review of arXiv:2509.07410}
}
read the original abstract

To support emerging mobile use cases (e.g., AR/VR, autonomous driving, and massive IoT), next-generation mobile cores for 5G and 6G are being re-architected as service-based architectures (SBAs) running on both private and public clouds. However, current performance optimization strategies for scaling these cores still revert to traditional NFV-based techniques, such as consolidating functions into rigid, monolithic deployments on dedicated servers. This raises a critical question: Is there an inherent tradeoff between flexibility and scalability in an SBA-based mobile core, where improving performance (and resiliency) inevitably comes at the cost of one or the other? To explore this question, we introduce resilient SBA microservices design patterns and state-management strategies, and propose TEGRA -- a high-performance, flexible, and scalable SBA-based mobile core. By leveraging the mobile core's unique position in the end-to-end internet ecosystem (i.e., at the last-mile edge), TEGRA optimizes performance without compromising adaptability. Our evaluation demonstrates that TEGRA achieves significantly lower latencies, processing requests 20x, 11x, and 1.75x faster than traditional SBA core implementations -- free5GC, Open5GS, and Aether, respectively -- all while matching the performance of state-of-the-art cores (e.g., CoreKube) while retaining flexibility. Furthermore, it reduces the complexity of deploying new features, requiring orders of magnitude fewer lines of code (LoCs) compared to existing cores.

Figures

Figures reproduced from arXiv: 2509.07410 by the authors.

Figure 1
Figure 1. To gain flexibility and agility, mobile cores have [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. Comparing (a) traditional, (b) state-of-the-art, and (c) our proposed SBA mobile core architectures. [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. The end-to-end latency of different control events using synthetic (a, b, c) and real (d) traces in Aether [ [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figures from the paper (7 more)
Figure 4
Figure 4. Figure 4: Inter-service delay in Aether: AMF ↔ UDM. and across SBA Cores for Different UE Events. In the SBA core, various UE events (e.g., Registration, PDU Session Es￾tablishment, and Service Requests) trigger different subsets of services (e.g., AMF, SMF, and NRF). Moreover, …
Figure 5
Figure 5. Figure 5: Overview of an SBA mobile core ecosystem (Aether [ [PITH_FULL_IMAGE:figures/full_fig_p006_5.png]
Figure 6
Figure 6. Figure 6: Mapping mobile core services (a) to TEGRA’s SBA-based microservices design patterns (b). executing a long-running routine that also maintains a soft state of the UEs’ context it is processing ( [PITH_FULL_IMAGE:figures/full_fig_p007_6.png]
Figure 7
Figure 7. Figure 7: Improvement in end-to-end control-plane latency with T [PITH_FULL_IMAGE:figures/full_fig_p010_7.png]
Figure 10
Figure 10. Figure 10: Comparison of failure handling between Aether and TEGRA for SR. DRSM prevents latency spikes during high churn or failures. Without DRSM, overhead increases by an average of 5.6 ms ± 2.4 ms per UE. 6.3.4 TEGRA is Resilient to Failures, Ensuring Consis￾tent Performance…
Figure 9
Figure 9. Figure 9: Inter-service delay for REG: AMF ↔ UDM. support with core pinning (following best practices). The configuration includes a maximum of 4 cores per service instance, with the desired CPU utilization set to 60% of the requested cores (∼2.5 cores). Additionally, we cap the…
Figure 11
Figure 11. Figure 11: Comparison of end-to-end control-plane latency between Aether and [PITH_FULL_IMAGE:figures/full_fig_p017_11.png]

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