AXLE: Coordinated Offloading with Asynchronous Back-Streaming in Computational Memory Systems

Ada Gavrilovska; Kangkyu Park; Kwangsik Shin; Suyeon Lee

REVIEW 4 major objections 5 minor 31 references

AXLE: Coordinated Offloading with Asynchronous Back-Streaming in Computational Memory Systems

T0 review · 4 major / 5 minor · reviewed 2026-08-03 · deepseek-v4-flash

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Pith's one-line read Letting a CXL memory device push results into host memory, instead of the host fetching them, overlaps computation with data movement and cuts end-to-end runtime by up to 50.4%.

desk verdict A genuinely new CXL offload protocol with a plausible 50% win—on the condition that a CXL Type 3 device can actually act as a DMA bus master, which the paper does not demonstrate. read the letter →

arxiv 2512.04449 v2 pith:GOABVNTP submitted 2025-12-04 cs.DC

Suyeon Lee , Kangkyu Park , Kwangsik Shin , Ada Gavrilovska This is my paper · ORCID

classification cs.DC

keywords CXLcomputationalmemorynear-memoryprocessingasynchronousback-streamingoffloadingdisaggregatedCXL.ioDMApipelining

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper's central claim is that partial offloading to CXL-based computational memory should be coordinated by having the device stream results back to the host, not by having the host fetch them. It proposes an asynchronous back-streaming protocol: a DMA engine on the CXL memory device writes partial results into host-local ring buffers while the device and host continue computing. A system built around this protocol is shown in simulation to cut end-to-end runtime by up to 50.4% versus remote polling and 49.1% versus bulk synchronous flow, and to reduce device and host idle time by 22x and 3.9x on average. The gain comes from turning a serialized load-response pipeline into overlapped, fine-grained execution, which matters for workloads like LLM attention blocks, graph analytics, KNN, and database filtering. This makes general-purpose computational memory usable for fine-grained offloads that existing mechanisms cannot serve efficiently.

What carries the argument

The central mechanism is the asynchronous back-streaming protocol, a split of data and control over CXL: data flows device-to-host via CXL.io DMA posted writes initiated by the device, while control flows host-to-device via low-overhead CXL.mem stores. Two host-local ring buffers—one for payload, one for metadata—let the host poll a single local tail pointer; each metadata entry stores a payload slot identifier, enabling gap-aware, out-of-order consumption. The enabling assumption is a DMA engine attached as a bus master on a CXL Type 3 device, which lets the device initiate the reverse transfer without changing the CXL protocol.

What would settle it

Measure on a real CXL Type 3 device with a bus-master DMA engine whether device-initiated CXL.io posted writes to host physical addresses complete at the assumed latency and preserve ordering relative to a following metadata-tail update; if writes are slow, reordered, or unsupported, the claimed overlap and idle-time reductions will not reproduce.

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Extended reading notes

Core claim

The authors first show that the two established offloading mechanisms are each lopsided. Remote polling over CXL.io allows asynchronous execution but carries polling intervals that dominate fine-grained tasks, while bulk synchronous flow over CXL.mem has low launch overhead but stalls the host until the remote kernel finishes and results are loaded. They then propose a third protocol. In asynchronous back-streaming, the computational memory device monitors its own result output and, once a configurable amount of data is ready, uses a DMA engine attached as a bus master on a CXL Type 3 device to issue CXL.io posted writes into host-local ring buffers. The host polls only a single local metada

Load-bearing premise

The whole result rests on a CXL memory device being able to initiate fast DMA writes into host memory by itself; if device-initiated CXL.io posted writes at the assumed 350 ns latency do not work on real hardware, the back-streaming mechanism cannot happen and the runtime gains disappear.

Editorial extensions

If this is right

Offloading fine-grained kernels (microsecond-scale attention blocks, distance computations, filters) becomes viable because notification cost is a local pointer poll rather than a CXL round-trip.
Host cores no longer stall on result loads; reported host idle time drops 3.85x on average, freeing those cores for other tasks or allowing fewer cores per server.
Data-movement-heavy workloads such as graph analytics see the largest gains, up to 50.4% end-to-end, because streaming hides the transfer behind compute.
The benefit depends on small streaming factors; batching results into large DMA transfers erodes overlap and can make the protocol slower than bulk synchronous flow.
Out-of-order streaming is required for the advertised gains: disabling it increases runtime by up to 2.28x under round-robin scheduling.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

If the assumed 350 ns device-initiated CXL.io write latency holds on real hardware, the protocol needs no new CXL feature, only a DMA engine with bus-master capability; the main unknown on the path to silicon is whether memory-fence ordering between payload writes and metadata-tail updates is preserved.
The authors leave implicit that back-streaming makes the host less sensitive to CXL link latency in general: only flow-control messages sit on the critical path, so slower or more congested links degrade overlap less than in fetch-based models.
A natural extension is an adaptive streaming factor and polling interval chosen per workload phase; the paper's experiments show both parameters have a strong effect on end-to-end runtime, so a self-tuning version of the proposed system should outperform fixed settings.
For LLM inference, the paper finds marginal gains when the host has few tasks and the final task tail dominates; a testable fix is splitting the last host task or batching multiple inference requests, which would expose the protocol's overlap in pipeline-shaped workloads.

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Signed reviews

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Quick take: worth reading for anyone working on CXL near-memory processing. It identifies a real limitation of existing offload mechanisms—synchronous result fetch stalls the host—and proposes a new protocol that has the device push results back via CXL.io DMA while using CXL.mem for control. That combination is new as far as I can tell, and the simulated results (up to 50% runtime reduction) are consistent with the design. But the whole thing rests on a hardware capability the paper does not establish: a CXL Type 3 device acting as a DMA bus master to write to host physical addresses. The paper only says it 'targets environments' where that exists, with no spec reference or silicon evidence. If that capability is not real, the protocol cannot work and the 50% number is moot.

What I liked: the motivation is solid. The idle-time analysis in Section III makes a clear case that both host and CCM stall in remote polling and bulk synchronous models. The ring-buffer design with separate metadata and payload, local polling, and flow control is clean. The out-of-order streaming support is a nice touch for integrating with existing schedulers. They also include an interrupt-based variant to justify why polling is necessary. And they are honest about the work being a preparatory simulation step.

Soft spots, in order: (1) the DMA bus master assumption is the linchpin. They don't cite a spec section or a device that does this. (2) Memory-fence ordering between payload writes and metadata tail updates is enforced in the simulator, not verified on any real CXL/PCIe ordering. (3) All results are single-run simulation outputs with no error bars, and the simulator is an extension of M2NDP with parameters chosen by the authors. (4) Sloppy consistency: title and abstract say AXLE, the body says KAI, with different headline numbers (14.53x vs 22.11x idle reduction). That probably comes from versioning but should be fixed.

If I were an editor, I'd send this to peer review. Reviewers should push for a concrete feasibility argument for the DMA capability, or evidence that such a device is coming. The idea is genuinely useful if the hardware materializes.

Referee Report

4 major / 5 minor

Summary. The paper studies partial offloading to CXL-based Computational Memory (CCM) devices. It contrasts two existing mechanisms: remote polling over CXL.io, which is asynchronous but high-overhead, and bulk synchronous flow over CXL.mem, which is low-overhead but blocks the host. It proposes asynchronous back-streaming, in which the CCM device uses a DMA engine to stream partial results into a host-local ring buffer, with local polling and flow control via CXL.mem writes. The KAI system implements this protocol on top of the M2NDP simulator. Evaluations on eight workloads claim up to 50.4% end-to-end runtime reduction and large idle-time reductions relative to the two baselines.

Significance. If the key hardware assumption—that a CXL Type 3 device can initiate CXL.io posted writes to host physical addresses through an attached DMA bus master—is valid, the paper identifies a genuine inefficiency in CCM offloading pipelines and offers a plausible, well-structured solution. The trade-off analysis in §III is useful, and the separation of metadata and payload ring buffers plus out-of-order streaming is a thoughtful systems design. The use of an open-source simulator and the detailed implementation description are strengths. However, the central quantitative claims rest on an unverified hardware capability and are validated only in a simulator; the paper is best read as a design study pending hardware confirmation.

major comments (4)

[IV-D] Section IV-D states: 'To enable device-initiated data transfers ... we target environments where a DMA engine is attached as a bus master on top of a CXL Type 3 device. In this configuration, payloads are transferred from the device to the host physical address via a CXL.io (PCIe) posted write.' This is the linchpin of the entire asynchronous back-streaming protocol: without this device-initiated DMA capability, the back-streaming shown in Fig. 1(c) and all subsequent gains (up to 50.4% in Fig. 10(e)) cannot occur. The paper gives no evidence that this configuration is permitted by the CXL specification, exists in any current CXL controller, or has been demonstrated in the authors' own FPGA prototype. The CXL.io latency is only configured as 350 ns in Table III. The authors should provide a concrete specification reference or prototype evidence, or explicitly label the results as conditi
[IV-C] The memory-correctness section asserts that 'our simulator implementation enforces this ordering and verifies functional correctness while running applications.' The critical ordering between payload writes and metadata tail updates is enforced only in the simulator. On real hardware, posted writes over PCIe/CXL.io do not guarantee this ordering without an explicit fence or completion mechanism. The paper should identify the specific hardware mechanism—e.g., a DMA write barrier, a read-after-write to the same location, or a CXL protocol rule—that enforces 'payload data write → metadata tail index update' on actual CXL devices. Without this, the consistency invariant is unsubstantiated and the ring-buffer protocol may expose partial or stale data to the host.
[V-A] The evaluation is based on a single simulation run for each configuration. The paper does not state whether the M2NDP simulator is deterministic, nor does it report error bars or confidence intervals. The DMA preparation time (500 ns) and CXL.io round-trip latency (350 ns) in Table III are assumed values with no sensitivity analysis. Since the paper's headline claims are precise quantitative reductions, the authors should either confirm that the simulator is deterministic and report the exact configuration, or, if stochastic, provide multiple runs with error bars. Sensitivity to the assumed DMA overhead should also be discussed, as it directly affects the claimed speedups.
[II] The paper itself states that 'this simulation-based research serves as a preparatory step toward realizing and validating the new data and control planes on an upcoming ASIC-based CCM device.' Thus, the abstract and conclusion's unqualified statements that KAI 'reduces end-to-end runtime by up to 50.4%' overstate what has been demonstrated. The quantitative gains should be presented as simulation estimates conditioned on the DMA hardware assumption, not as measured system performance. Weighing the manuscript's own admission, this is a load-bearing limitation for the central claim.

minor comments (5)

[Abstract vs. body] The system is called AXLE in the abstract and arXiv title, but KAI throughout the body. The abstract also reports '50.14%' while §VII reports '50.4%'. These inconsistencies should be reconciled.
[Table III] The 'DMA preparation time per request: 500 ns' parameter is given without a source or measurement. Please add a justification or reference.
[Figure 10(h)] The LLM case is an important negative result where KAI provides little benefit. Consider discussing this case more prominently in the conclusion to temper the general claims.
[IV-D] The related-work discussion could cite existing CXL ordering rules or DMA implementations on CXL devices to strengthen the motivation in §IV-D.
[IV-C] The description of the 'visibility problem' would benefit from a short example or pseudo-code for the ring-buffer head/tail arithmetic, as the current text is dense.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the 50.4% claim is a simulator output produced from explicitly configured latencies, not a fitted or self-referential quantity.

full rationale

The paper's central result — KAI reducing end-to-end runtime by up to 50.4% and idle times by 22.11x/3.85x — is obtained from cycle-level simulation on the M2NDP simulator (Section V). No equation in the paper fits a parameter to the target result and then re-presents it as a prediction. The DMA latency (350 ns), polling intervals, and DMA preparation time (500 ns) are configured assumptions in Table III, not constants fitted to reproduce the claimed reductions. The key hardware precondition — a DMA engine attached as a bus master to a CXL Type 3 device — is stated as a targeted environment in Section IV-D ('we target environments where a DMA engine is attached as a bus master on top of a CXL Type 3 device'), not derived from the results. This is an unverified feasibility assumption and a correctness risk, but it is not circular: if the hardware cannot perform device-initiated CXL.io posted writes, the results fail, but the simulation still derives its outputs from that explicitly stated premise rather than from the outputs themselves. The paper also openly labels the work a 'preparatory step toward realizing and validating the new data and control planes on an upcoming ASIC-based CCM device' (Section II), which further clarifies that hardware validation is pending, not hidden. The self-citations to [19] and [31] (sharing authors with this paper) are used only to motivate graph-analytics offloading and frontier-dependency observations (Sections III-B, III-C); they are not used to justify the asynchronous back-streaming protocol or to supply its predicted performance, so they are not load-bearing. The M2NDP baseline itself is an external open-source simulator [9] cited as independent support. Memory-fence ordering is asserted and verified only in the simulator (Section IV-C), which is a validation limitation, but no circular step reduces a prediction to its own inputs. Overall, no derivation chain in the paper equates a fitted input with a claimed prediction or imports a self-authored uniqueness theorem to force the design. The appropriate finding is no significant circularity.

Assumptions & free parameters 5 free parameters · 5 assumptions · 2 invented entities

The design pulls several load-bearing assumptions from simulator validity and unverified hardware capabilities. Free parameters such as DMA prep time, polling interval, and streaming factor materially affect the reported gains; the paper's own sensitivity experiments show the headline improvement shrinks or reverses under alternative settings.

free parameters (5)

DMA preparation time per request = 500 ns
Table III assumption; directly sets per-back-stream overhead and would change all end-to-end numbers if wrong.
Local polling interval (default p1) = 50 ns
Default chosen in evaluation; extending to 5 us reduces or eliminates the benefit (Fig. 10), so the claim is sensitive to this assumed cost.
Streaming factor (SF1 default) = 32 B
SF is configurable; Fig. 13 shows large SF can make KAI slower than BS, so headline gains depend on a small streaming factor.
CXL.io / CXL.mem round-trip latencies = 350 ns / 70 ns
Table III config; the paper says it 'configured sufficiently long CXL.io protocol latency' rather than measuring it on real hardware.
Interrupt handling time (KAI_Interrupt baseline) = 50 us
Taken from [7] to construct a straw-man baseline; not validated in this system and used to dismiss interrupt-based notification.

assumptions (5)

domain assumption A CXL Type 3 device can host a DMA engine that writes host physical memory via CXL.io posted writes
Section IV-D: 'we target environments where a DMA engine is attached as a bus master...' No spec citation or hardware proof; load-bearing for the entire protocol.
domain assumption M2NDP simulator is a valid CCM model and can faithfully represent the new DMA/control plane
Sections II and V-A rely on the open-source simulator's validity; KAI-specific components are not validated against hardware.
domain assumption Memory fences in the simulator enforce the required ordering invariants
Section IV-C: 'Our simulator implementation enforces this ordering and verifies functional correctness' — correctness is asserted, not formally proven or hardware-tested.
domain assumption Cache-bypass pinned DMA regions do not hurt performance
Sections IV-C and IV-D assume streamed data has no temporal locality, so bypassing the cache is free.
domain assumption The eight evaluated workloads and their offloading targets represent the design space
Section V-A / Table IV; drawn from prior studies, with no coverage argument or sensitivity analysis over other domains.

invented entities (2)

KAI DMA executor
purpose: Monitors CCM result population, forms payload/metadata, and triggers CXL.io DMA back-streaming
Only implemented inside the simulator; no hardware or prototype evidence is provided.
Metadata/payload ring-buffer pair in host DMA region
purpose: Provides local notification and data staging to avoid remote polling and synchronous result loads
A design component; correctness and overhead are asserted via simulator memory fences, not measured on real hardware.

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Cite this review

Pith. "Pith review of AXLE: Coordinated Offloading with Asynchronous Back-Streaming in Computational Memory Systems." pith.science (2026). https://pith.science/paper/GOABVNTP

@misc{pith2026251204449,
  author       = {Pith},
  title        = {Pith review of: AXLE: Coordinated Offloading with Asynchronous Back-Streaming in Computational Memory Systems},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/GOABVNTP}},
  note         = {Machine review of arXiv:2512.04449}
}

read the original abstract

CXL-based Computational Memory (CCM) enables near-memory processing within expanded remote memory, offering opportunities to address data movement costs in disaggregated memory systems and to accelerate overall performance. However, existing offloading mechanisms do not fully leverage the trade-offs of different offload models based on different CXL protocols. This work first examines these tradeoffs and their impact on end-to-end performance and system efficiency for workloads with diverse data and computation characteristics. We propose Asynchronous Back-Streaming, a new offloading protocol that coordinates CXL.io and CXL.mem to enable result back-streaming and asynchronous pipelining across CCM and host tasks. We further design AXLE, a system that realizes this protocol with lightweight host-CCM interaction. Overall, AXLE reduces end-to-end runtime by up to 50.14%, reduces CCM and host idle times by an average of 14.53x and 3.93x, respectively, and achieves up to 6x reduction in host core stall time.

Figures

Figures reproduced from arXiv: 2512.04449 by the authors.

**Figure 2.** Block diagram of a real prototype of CCM device. The device appears [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗

**Figure 3.** Kernels of the attention block in LLM inference, exhibiting different [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗

Figures from the paper (9 more)

**Figure 5.** Figure 5: Execution of KNNs (Ddim, RnumRows) and graph analytics on M2NDP, using remote polling (RP) and bulk synchronous flow (BS) as offloading mechanisms. Normalized runtime ratios are shown as stacked bars for CCM tasks (purple), data movement (yellow), and host tasks (green…

**Figure 7.** Figure 7: Comparison of end-to-end runtime and two types of idle time for the [PITH_FULL_IMAGE:figures/full_fig_p005_7.png]

**Figure 8.** Figure 8: Overview of KAI components built on top of M [PITH_FULL_IMAGE:figures/full_fig_p006_8.png]

**Figure 9.** Figure 9: Detailed example flow of the asynchronous back-streaming protocol [PITH_FULL_IMAGE:figures/full_fig_p007_9.png]

**Figure 10.** Figure 10: Normalized end-to-end runtime ratio for baselines, KAI variants with interrupt-based notification, and KAI (polling factors: p1 = 50 ns, p10 = 500 [PITH_FULL_IMAGE:figures/full_fig_p010_10.png]

**Figure 11.** Figure 11: Different LLM-case results under modified hardware configurations: [PITH_FULL_IMAGE:figures/full_fig_p010_11.png]

**Figure 12.** Figure 12: Normalized idle time ratio for baselines and KAI when using a p10 local polling factor. [PITH_FULL_IMAGE:figures/full_fig_p011_12.png]

**Figure 13.** Figure 13: Normalized end-to-end runtime of KAI and baselines relative to SF1, [PITH_FULL_IMAGE:figures/full_fig_p011_13.png]

**Figure 14.** Figure 14: Normalized end-to-end runtime of KAI when running different [PITH_FULL_IMAGE:figures/full_fig_p011_14.png]

Discussion (0). Continue with ORCID to comment.

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Computational cxl-memory solution for accel- erating memory-intensive applications,

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Demystifying cxl memory with genuine cxl-ready systems and devices,

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Clay: Cxl-based scalable ndp architecture accelerating embedding layers,

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Fam-graph: Graph analytics on disag- gregated memory,

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Pith tools

Reviewed August 3, 2026 · model on record in the stance chip above.

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An introduction to the compute express link (cxl) interconnect,

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2024