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arxiv: 2604.05308 · v1 · submitted 2026-04-07 · 💻 cs.AR

PHAROS: Pipelined Heterogeneous Accelerators for Real-time Safety-critical Systems With Deadline Compliance

Shixin Ji , Jinming Zhuang , Sarah Schultz , Zhuoping Yang , Xingzhen Chen , Zheng Dong , Alex K. Jones , Yihui Ren
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Peipei Zhou
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Pith reviewed 2026-05-10 19:40 UTC · model grok-4.3

classification 💻 cs.AR
keywords heterogeneous acceleratorsreal-time systemsdesign space explorationschedulability analysispreemption mechanismssafety-critical systemsFIFO schedulingEDF scheduling
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The pith

PHAROS shows that adding soft real-time schedulability to accelerator design exploration finds workable hardware setups for more task sets than throughput-only methods.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

PHAROS is a design framework for spatially partitioned heterogeneous accelerators that centers optimization on meeting real-time deadlines rather than maximizing speed. It adds preemption support and scheduler designs for FIFO and EDF policies, then runs a custom design space exploration that uses soft real-time schedulability as its main objective and constraint. Across evaluations on diverse applications the method identifies feasible hardware configurations for a wider range of task sets and achieves better deadline compliance than baselines focused only on throughput. The work also supplies response-time analyses for the supported schedulers. This matters in safety-critical embedded systems where timely execution directly affects overall safety.

Core claim

Through modeling, analysis, and evaluation, PHAROS demonstrates that its soft real-time schedulability-oriented design space exploration discovers more feasible configurations for a broader range of task sets than throughput-oriented DSE baselines while delivering improved real-time performance; the framework introduces preemption mechanisms and scheduler designs for spatially partitioned heterogeneous accelerators under FIFO and EDF policies and provides response-time analyses for those algorithms.

What carries the argument

Soft real-time (SRT) schedulability-oriented design space exploration (DSE) that tailors objectives and constraints to schedulability, paired with preemption mechanisms for spatially partitioned heterogeneous accelerators under FIFO and EDF scheduling.

If this is right

  • A wider variety of task sets from safety-critical applications can be scheduled without missing deadlines.
  • Hardware configurations can be selected to provide stronger guarantees on execution predictability.
  • Designers can optimize accelerator systems specifically for real-time constraints instead of average-case throughput.
  • Response-time bounds become available for FIFO and EDF schedulers running on these accelerators.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same schedulability-driven exploration approach could be extended to hard real-time constraints by strengthening the underlying analyses.
  • Future accelerator hardware designs might incorporate the preemption features as standard primitives once overheads are quantified.
  • Similar real-time-aware design space exploration may prove useful for other embedded platforms such as GPUs or reconfigurable fabrics.

Load-bearing premise

The introduced preemption mechanisms and soft real-time schedulability analysis for spatially partitioned heterogeneous accelerators can be realized in hardware without significant unmodeled overheads or interference that would invalidate the deadline guarantees.

What would settle it

A hardware implementation of the preemption mechanisms on a spatially partitioned heterogeneous accelerator, with measurements showing whether task sets predicted as schedulable by the analysis actually meet all deadlines under realistic interference.

Figures

Figures reproduced from arXiv: 2604.05308 by Alex K. Jones, Jinming Zhuang, Peipei Zhou, Sarah Schultz, Shixin Ji, Xingzhen Chen, Yihui Ren, Zheng Dong, Zhuoping Yang.

Figure 1
Figure 1. Figure 1: Comparing SRT-schedulability of different DSE [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: PHAROS hardware architecture. deadline compliance for tasksets with smaller periods, whereas these frameworks fail due to hardware inefficiency. Real-time theories for guiding accelerator design: To en￾sure deadline compliance, the accelerator design must be paired with real-time theories to analyze schedulability or response time. For a single accelerator, [27] gives the earliest formulation in the HRT sc… view at source ↗
Figure 3
Figure 3. Figure 3: Preemption pattern and overhead modeling. [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: PHAROS design space exploration. of computing a tile, storing, and loading the buffers are fixed in one accelerator and are only related to its design parameters: 𝜉 𝑘 𝑖 = 𝑒 𝑘 𝑡𝑖𝑙𝑒 + 𝑒 𝑘 𝑠𝑡𝑜𝑟𝑒 + 𝑒 𝑘 𝑙𝑜𝑎𝑑 (5) Where 𝑒 𝑘 𝑡𝑖𝑙𝑒 ,𝑒 𝑘 𝑠𝑡𝑜𝑟𝑒 , and 𝑒 𝑘 𝑙𝑜𝑎𝑑 are functions of 𝐴 𝑘 , ..., 𝑍𝑘 . Specifically, when this accelerator is skipped (𝑏 𝑘 𝑖 = 0), the 𝑒 𝑘 𝑖 is also 0. The preemption only happens when EDF scheduling… view at source ↗
Figure 5
Figure 5. Figure 5: Beam search progress. thus reducing the period results in a higher maximum speed in the system. When scaling down all periods proportionally to x%, the utilization of all accelerators will increase to 1 𝑥% . Thus, the potential of one system to further scale down the periods without 𝑢 > 1 is determined by the maximum utilization of the accelerators. 4.2 Beam Search Heuristics One significant challenge in P… view at source ↗
Figure 6
Figure 6. Figure 6: SRT-schedulable taskset design points of SRT-guided (SG) and throughput-guided (TG) EDF using FIFO and EDF [PITH_FULL_IMAGE:figures/full_fig_p005_6.png] view at source ↗
Figure 9
Figure 9. Figure 9: Search time comparison of various beam search se [PITH_FULL_IMAGE:figures/full_fig_p006_9.png] view at source ↗
Figure 8
Figure 8. Figure 8: The response time statistics of FIFO vs. EDF sched [PITH_FULL_IMAGE:figures/full_fig_p006_8.png] view at source ↗
read the original abstract

Spatially partitioned heterogeneous accelerators (HAs) are increasingly adopted in embedded systems for their performance and flexibility. Yet most existing HA design frameworks optimize primarily for throughput or quality-of-service (QoS) metrics. They often overlook safety-critical real-time requirements, including hardware support for predictable execution, real-time-aware design space exploration (DSE), and rigorous schedulability analysis. These requirements are essential in safety-critical applications such as smart transportation, where schedulability guarantees directly affect system safety. To address this gap, we present PHAROS, a real-time-centric HA design framework. PHAROS introduces preemption mechanisms and scheduler designs for spatially partitioned HAs under first-in-first-out (FIFO) and earliest-deadline-first (EDF) policies. Leveraging modern real-time theory, we further develop a soft real-time (SRT) schedulability-oriented DSE with objectives and constraints tailored to SRT schedulability. Through comprehensive modeling, analysis, and evaluation across diverse applications, we show that PHAROS's DSE discovers more feasible configurations for a broader range of task sets than throughput-oriented DSE baselines while delivering improved real-time performance. We also provide response-time analyses for the supported scheduling algorithms.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

1 major / 2 minor

Summary. The paper presents PHAROS, a real-time-centric framework for designing spatially partitioned heterogeneous accelerators (HAs). It introduces hardware preemption mechanisms and scheduler designs supporting FIFO and EDF policies, develops an SRT schedulability-oriented design space exploration (DSE) with tailored objectives and constraints, and supplies response-time analyses for the supported algorithms. The central claim is that PHAROS's DSE identifies more feasible task-set configurations across a broader range of applications than throughput-oriented DSE baselines while delivering improved real-time performance and deadline compliance.

Significance. If the response-time analyses are sound and the DSE evaluations demonstrate the claimed advantages without unmodeled overheads, the work would be significant for safety-critical embedded systems. It bridges HA design with modern real-time theory to enable predictable execution on flexible accelerators, directly addressing gaps in current frameworks that prioritize throughput over schedulability guarantees.

major comments (1)
  1. [Response-time analyses] Response-time analyses section: the SRT analyses for FIFO/EDF preemption on spatially partitioned HAs must explicitly bound or prove negligible all hardware-specific overheads (context save/restore, partial reconfiguration latency, pipeline state, and cross-partition memory contention); without this, the computed response times are optimistic and the DSE feasibility results cannot guarantee deadline compliance in silicon.
minor comments (2)
  1. [Abstract] Abstract: the claim of 'comprehensive modeling, analysis, and evaluation across diverse applications' is stated without any quantitative summary (e.g., number of task sets, improvement percentages, or feasibility ratios); a concise results highlight would improve clarity.
  2. [Evaluation] Evaluation: ensure all reported comparisons include the specific task-set parameters, number of runs, and any statistical measures so that the superiority over throughput baselines can be independently assessed.

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for the constructive review and the recommendation for major revision. The feedback highlights an important aspect of ensuring the soundness of our response-time analyses for safety-critical use. We address the major comment below and commit to the necessary revisions.

read point-by-point responses

  1. Referee: [Response-time analyses] Response-time analyses section: the SRT analyses for FIFO/EDF preemption on spatially partitioned HAs must explicitly bound or prove negligible all hardware-specific overheads (context save/restore, partial reconfiguration latency, pipeline state, and cross-partition memory contention); without this, the computed response times are optimistic and the DSE feasibility results cannot guarantee deadline compliance in silicon.

    Authors: We agree that explicit bounds on hardware-specific overheads are required for the analyses to be non-optimistic and to support deadline-compliance guarantees. Our current response-time analyses for FIFO and EDF on spatially partitioned HAs model preemption costs and pipeline behavior at a high level, but we acknowledge that we have not derived or stated explicit upper bounds for all listed items (partial reconfiguration latency, pipeline state, and cross-partition memory contention). In the revised manuscript we will augment the Response-time analyses section with these bounds, using the hardware parameters already defined in the PHAROS model, or provide arguments for their negligibility under the stated assumptions. This change will directly strengthen the link between the DSE feasibility results and practical deadline compliance. revision: yes

Circularity Check

0 steps flagged

No significant circularity in PHAROS derivation chain

full rationale

The paper introduces hardware preemption mechanisms for spatially partitioned HAs and develops SRT schedulability-oriented DSE plus response-time analyses by extending cited modern real-time theory. No load-bearing step reduces by construction to a fitted input, self-definition, or self-citation chain; the modeling, constraints, and evaluation across applications remain independent of the target claims. This is the expected non-finding for a framework paper that adds HA-specific mechanisms on top of established schedulability results.

Axiom & Free-Parameter Ledger

0 free parameters · 2 axioms · 0 invented entities

Only the abstract is available, so the ledger is necessarily incomplete; no explicit free parameters or invented entities are named, but the framework rests on domain assumptions about hardware modeling and real-time theory applicability.

axioms (2)
  • domain assumption Spatially partitioned heterogeneous accelerators can support preemption mechanisms under FIFO and EDF scheduling policies.
    Foundational to the introduced scheduler designs and preemption support.
  • domain assumption Soft real-time schedulability metrics can serve as primary objectives and constraints for design space exploration of accelerators.
    Directly stated as the basis for the SRT schedulability-oriented DSE.

pith-pipeline@v0.9.0 · 5544 in / 1466 out tokens · 77684 ms · 2026-05-10T19:40:42.964653+00:00 · methodology

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Reference graph

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