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arxiv: 2604.08758 · v2 · submitted 2026-04-09 · 📡 eess.SY · cs.SY

An Asynchronous Delta Modulator for Spike Encoding in Event-Driven Brain-Machine Interface

Kaushik Lakshmiramanan , Vineeta Nair , Ching-Yi Lin , Sheng-Yu Peng , Sahil Shah This is my paper

Pith reviewed 2026-05-10 16:49 UTC · model grok-4.3

classification 📡 eess.SY cs.SY
keywords asynchronous delta modulatorspike encodingneuromorphic front-endbrain-machine interfaceevent-driven neural recording65nm CMOSspiking neural networksbiopotential compression
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The pith

An asynchronous delta modulator converts analog neural signals into ON and OFF spikes using 60.73 nJ per spike in 65nm CMOS.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper presents the design and silicon implementation of an asynchronous delta modulator as a neuromorphic front-end for event-driven neural recording. It converts continuous analog biopotential signals into discrete asynchronous ON and OFF spikes that compress the data into spike trains compatible with spiking neural networks. This asynchronous approach is positioned to support real-time decoding in closed-loop brain-machine interfaces through direct integration with neuromorphic hardware. Measurements from the fabricated 65nm CMOS chip report an energy consumption of 60.73 nJ per spike, an F1-score of 80 percent relative to a behavioral model, and a compact pixel area of 73.45 by 73.64 micrometers. A sympathetic reader would care because the encoding promises lower power and event-driven operation suitable for implantable neural interfaces.

Core claim

The asynchronous delta modulator converts analog signals into discrete, asynchronous ON and OFF spikes, effectively compressing continuous biopotentials into spike trains compatible with spiking neural networks. Its asynchronous operation enables seamless integration with neuromorphic architectures for real-time decoding in closed-loop brain-machine interfaces. Fabricated in 65nm CMOS, the circuit consumes 60.73 nJ/spike with an F1-score of 80% compared to its behavioral model and occupies a compact area of 73.45 μm × 73.64 μm.

What carries the argument

The asynchronous delta modulator, a circuit that detects changes in analog input beyond a threshold to produce discrete ON and OFF spikes, carrying the argument by turning continuous signals into event-driven spike trains.

If this is right

  • The spike trains compress neural data for more efficient transmission and processing in neural interfaces.
  • Energy use of 60.73 nJ per spike supports extended battery life in implantable brain-machine interface devices.
  • Direct compatibility with spiking neural networks allows the encoded signals to be used without intermediate conversion steps.
  • The compact pixel size of 73.45 by 73.64 micrometers enables high-density arrays for multi-channel neural recording.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • If the spikes integrate directly with SNNs, overall system power could drop by eliminating continuous analog-to-digital sampling.
  • Testing the modulator outputs with actual in-vivo neural recordings in a full closed-loop setup would provide concrete evidence of real-time decoding performance.
  • The asynchronous design may reduce feedback latency in brain-machine interface applications compared to clocked sampling methods.

Load-bearing premise

The ON and OFF spikes will enable seamless integration with neuromorphic architectures for real-time decoding in closed-loop brain-machine interfaces without further validation shown in the results.

What would settle it

Feeding the modulator's spike trains into an SNN decoder and measuring decoding accuracy below the reported 80% F1-score on the original biopotential signals would falsify the claim of effective compatibility.

Figures

Figures reproduced from arXiv: 2604.08758 by Ching-Yi Lin, Kaushik Lakshmiramanan, Sahil Shah, Sheng-Yu Peng, Vineeta Nair.

Figure 1
Figure 1. Figure 1: Proposed method in a closed-loop BMI and SNN decoding perfor [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Single action potential encoded using the asynchronous delta modu [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: (a) System-level block diagram of the asynchronous delta modulator [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: (a) Taped-out chip (b) Enlarged view of the asynchronous delta [PITH_FULL_IMAGE:figures/full_fig_p003_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Transient response showing the analog input waveform ( [PITH_FULL_IMAGE:figures/full_fig_p004_5.png] view at source ↗
read the original abstract

This paper presents the design and implementation of an asynchronous delta modulator as a spike encoder for event-driven neural recording in a 65nm CMOS process. The proposed neuromorphic front-end converts analog signals into discrete, asynchronous ON and OFF spikes, effectively compressing continuous biopotentials into spike trains compatible with spiking neural networks (SNNs). Its asynchronous operation enables seamless integration with neuromorphic architectures for real-time decoding in closed-loop brain-machine interfaces (BMIs). Measurement results from silicon demonstrate an energy consumption of 60.73 nJ/spike, an F1-score of 80% compared to a behavioral model of the asynchronous delta modulator, and a compact pixel area of 73.45 um $\times$ 73.64 um.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 0 minor

Summary. This paper presents the design and silicon implementation of an asynchronous delta modulator in a 65 nm CMOS process for spike encoding of analog biopotentials in event-driven brain-machine interfaces. The neuromorphic front-end generates asynchronous ON and OFF spikes, with reported silicon measurements of 60.73 nJ/spike energy consumption, 80% F1-score against a behavioral model, and a compact area of 73.45 μm × 73.64 μm.

Significance. Should the silicon characterization prove robust, the work offers a low-energy, area-efficient spike encoder that compresses continuous signals into event-based representations suitable for spiking neural networks. This could support power-constrained neuromorphic BMIs. The provision of physical measurements from a fabricated 65 nm CMOS chip is a strength, supplying concrete data rather than simulations alone. However, the absence of any end-to-end results with SNN decoders limits evaluation of the practical impact on real-time closed-loop applications.

major comments (2)
  1. [Abstract] Abstract: The key performance metrics (60.73 nJ/spike energy and 80% F1-score) are stated without information on test conditions, sample size, error bars, or comparisons to baselines or prior encoders; this leaves the support for the silicon results incomplete.
  2. [Abstract] Abstract: The claim that asynchronous operation 'enables seamless integration with neuromorphic architectures for real-time decoding in closed-loop brain-machine interfaces' is not supported by experimental evidence; the manuscript provides only standalone modulator characterization with no SNN decoding, latency, or closed-loop BMI task results.

Simulated Author's Rebuttal

2 responses · 1 unresolved

We thank the referee for the constructive feedback and for recognizing the value of the silicon measurements. We address the two major comments on the abstract below. We will revise the manuscript to improve clarity and qualify claims where appropriate.

read point-by-point responses

  1. Referee: [Abstract] Abstract: The key performance metrics (60.73 nJ/spike energy and 80% F1-score) are stated without information on test conditions, sample size, error bars, or comparisons to baselines or prior encoders; this leaves the support for the silicon results incomplete.

    Authors: We agree the abstract would benefit from added context. Space constraints limit detail, but test conditions (synthetic biopotentials and recorded neural signals), measurement repetitions across dies, and comparisons to prior encoders appear in Sections IV and V. The F1-score specifically validates silicon against the behavioral model. We will revise the abstract to note 'measured in 65 nm CMOS with biopotential inputs' for better support. revision: yes

  2. Referee: [Abstract] Abstract: The claim that asynchronous operation 'enables seamless integration with neuromorphic architectures for real-time decoding in closed-loop brain-machine interfaces' is not supported by experimental evidence; the manuscript provides only standalone modulator characterization with no SNN decoding, latency, or closed-loop BMI task results.

    Authors: The work centers on the front-end encoder characterization; no SNN decoding or closed-loop results are included. The abstract statement describes the design intent and spike-format compatibility with neuromorphic systems, as outlined in the introduction. We will revise the abstract to qualify the language (e.g., 'designed to enable' or 'supports potential integration') to match the presented scope. revision: yes

standing simulated objections not resolved
  • We do not have experimental SNN decoding, latency, or closed-loop BMI results, as these were outside the scope of the current study focused on the modulator front-end.

Circularity Check

0 steps flagged

No circularity: hardware measurements with no derivation chain

full rationale

The paper is an engineering implementation report on a fabricated 65 nm CMOS asynchronous delta modulator. It states design goals (analog-to-spike conversion for SNN compatibility) and reports direct silicon measurements (60.73 nJ/spike, 80 % F1-score vs. its own behavioral model, pixel area). No equations, parameter fits, predictions, or mathematical derivations appear in the abstract or description. The F1-score is a straightforward validation metric between fabricated hardware and a separate behavioral simulation of the same circuit; it does not constitute a fitted input renamed as a prediction. No self-citations, uniqueness theorems, or ansatzes are invoked. The integration claim is a design assertion supported by the measured spike output, not a derived result that reduces to the paper's own inputs.

Axiom & Free-Parameter Ledger

0 free parameters · 2 axioms · 0 invented entities

The central claim rests on standard domain assumptions about delta modulation for analog-to-spike conversion and the compatibility of asynchronous spikes with SNNs; no free parameters or new entities are introduced.

axioms (2)
  • domain assumption Delta modulation principles convert continuous signals to discrete events based on threshold crossings
    The design directly applies established asynchronous delta modulation without new proof.
  • domain assumption Asynchronous ON/OFF spikes are compatible with spiking neural networks for BMI decoding
    Assumed to enable seamless integration as stated in the abstract.

pith-pipeline@v0.9.0 · 5438 in / 1457 out tokens · 72865 ms · 2026-05-10T16:49:58.230285+00:00 · methodology

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Reference graph

Works this paper leans on

24 extracted references · 24 canonical work pages

  1. [1]

    Flexible high- density microelectrode arrays for closed-loop brain–machine interfaces: a review,

    X. Liu, Y . Gong, Z. Jiang, T. Stevens, and W. Li, “Flexible high- density microelectrode arrays for closed-loop brain–machine interfaces: a review,”Frontiers in Neuroscience, vol. 18, p. 1348434, 2024

    work page 2024

  2. [2]

    How advances in neural recording affect data analysis,

    I. H. Stevenson and K. P. Kording, “How advances in neural recording affect data analysis,”Nature neuroscience, vol. 14, no. 2, pp. 139–142, Feb. 2011. [Online]. Available: https://www.ncbi.nlm.nih.gov/pmc/articles/PMC3410539/

    work page 2011

  3. [3]

    A Survey of Neural Front End Amplifiers and Their Requirements toward Practical Neural Interfaces,

    E. Bharucha, H. Sepehrian, and B. Gosselin, “A Survey of Neural Front End Amplifiers and Their Requirements toward Practical Neural Interfaces,”Journal of Low Power Electronics and Applications, vol. 4, no. 4, pp. 268–291, 2014

    work page 2014

  4. [4]

    A 2 × 2 Neural Amplifier Macro-Pixel with Shared DC Servo Loop for High- Density Brain-Computer Interfaces,

    B. H. Abdelgaliel, M. Exalto, Y .-H. Ou-Yang, and D. G. Muratore, “A 2 × 2 Neural Amplifier Macro-Pixel with Shared DC Servo Loop for High- Density Brain-Computer Interfaces,” in2024 IEEE Biomedical Circuits and Systems Conference (BioCAS), Oct. 2024, pp. 1–5, iSSN: 2766- 4465

    work page 2024

  5. [5]

    A Compact, Low-Noise, Chopped Front-End for Peripheral Nerve Recording in 180 nm CMOS,

    J. Liu and R. M. Walker, “A Compact, Low-Noise, Chopped Front-End for Peripheral Nerve Recording in 180 nm CMOS,” in2018 IEEE Biomedical Circuits and Systems Conference (BioCAS), Oct. 2018, pp. 1–4, iSSN: 2163-4025. [Online]. Available: https://ieeexplore.ieee.org/document/8584716/

    work page arXiv 2018

  6. [6]

    A high-performance neural prosthesis enabled by control algorithm design,

    V . Gilja, P. Nuyujukian, C. A. Chestek, J. P. Cunningham, B. M. Yu, J. M. Fan, M. M. Churchland, M. T. Kaufman, J. C. Kao, S. I. Ryu, and K. V . Shenoy, “A high-performance neural prosthesis enabled by control algorithm design,”Nature Neuroscience, vol. 15, no. 12, pp. 1752–1757, Dec. 2012. [Online]. Available: https://www.nature.com/articles/nn.3265

    work page 2012

  7. [7]

    Comparison of spike sorting and thresholding of voltage waveforms for intracortical brain-machine interface performance,

    B. P. Christie, D. M. Tat, Z. T. Irwin, V . Gilja, P. Nuyujukian, J. D. Foster, S. I. Ryu, K. V . Shenoy, D. E. Thompson, and C. A. Chestek, “Comparison of spike sorting and thresholding of voltage waveforms for intracortical brain-machine interface performance,”Journal of Neural Engineering, vol. 12, no. 1, p. 016009, Feb. 2015

    work page 2015

  8. [8]

    Decoding grasp and speech signals from the cortical grasp circuit in a tetraplegic human,

    S. K. W ANDELT, S. KELLIS, D. A. BJ ˚ANES, K. PEJSA, B. LEE, C. LIU, and R. A. ANDERSEN, “Decoding grasp and speech signals from the cortical grasp circuit in a tetraplegic human,”Neuron, vol. 110, no. 11, pp. 1777–1787.e3, Jun. 2022. [Online]. Available: https://pmc.ncbi.nlm.nih.gov/articles/PMC9186423/

    work page 2022

  9. [9]

    Spike sorting algorithms and their efficient hardware im- plementation: a comprehensive survey,

    T. Zhang, M. Rahimi Azghadi, C. Lammie, A. Amirsoleimani, and R. Genov, “Spike sorting algorithms and their efficient hardware im- plementation: a comprehensive survey,”Journal of Neural Engineering, vol. 20, no. 2, p. 021001, Apr. 2023

    work page 2023

  10. [10]

    L-Sort: On-chip Spike Sorting with Efficient Median-of-Median Detection and Localization-based Clustering,

    Y . Han, Y . Pan, X. Jiang, C. Sestito, S. Agwa, T. Prodromakis, and S. Wang, “L-Sort: On-chip Spike Sorting with Efficient Median-of-Median Detection and Localization-based Clustering,” Jan. 2025, arXiv:2501.17885 [eess]. [Online]. Available: http://arxiv.org/abs/2501.17885

    work page arXiv 2025

  11. [11]

    Validation of adaptive threshold spike detector for neural recording,

    P. Watkins, G. Santhanam, K. Shenoy, and R. Harrison, “Validation of adaptive threshold spike detector for neural recording,” inThe 26th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, vol. 2, 2004, pp. 4079–4082

    work page 2004

  12. [12]

    Adaptive threshold neural spike detector using stationary wavelet transform in cmos,

    Y . Yang, C. S. Boling, A. M. Kamboh, and A. J. Mason, “Adaptive threshold neural spike detector using stationary wavelet transform in cmos,”IEEE Transactions on Neural Systems and Rehabilitation Engi- neering, vol. 23, no. 6, pp. 946–955, 2015

    work page 2015

  13. [13]

    A 128×128 120 db 15µs latency asynchronous temporal contrast vision sensor,

    P. Lichtsteiner, C. Posch, and T. Delbruck, “A 128×128 120 db 15µs latency asynchronous temporal contrast vision sensor,”IEEE Journal of Solid-State Circuits, vol. 43, no. 2, pp. 566–576, 2008

    work page 2008

  14. [14]

    A spiking neural network with continuous local learning for robust online brain machine interface,

    E. A. Taeckens and S. Shah, “A spiking neural network with continuous local learning for robust online brain machine interface,”Journal of Neural Engineering, vol. 20, no. 6, p. 066042, Jan. 2024

    work page 2024

  15. [15]

    Cavedon, B

    J. Dethier, P. Nuyujukian, S. I. Ryu, K. V . Shenoy, and K. Boahen, “Design and validation of a real-time spiking-neural-network decoder for brain–machine interfaces,”Journal of Neural Engineering, vol. 10, no. 3, p. 036008, Apr. 2013. [Online]. Available: https://doi.org/10.1088/1741- 2560/10/3/036008

    work page doi:10.1088/1741- 2013

  16. [16]

    Architectural Exploration of Hybrid Neural Decoders for Neuromorphic Implantable BMI,

    V . Mohan, B. Zhou, Z. Wang, A. Bharath, E. Drakakis, and A. Basu, “Architectural Exploration of Hybrid Neural Decoders for Neuromorphic Implantable BMI,” in2025 IEEE International Symposium on Circuits and Systems (ISCAS), May 2025, pp. 1–5. [Online]. Available: https://ieeexplore.ieee.org/abstract/document/11043277

    work page arXiv 2025

  17. [17]

    Nonhuman primate reaching with multichannel sensorimotor cortex electrophysiology,

    J. E. O’Doherty, M. M. B. Cardoso, J. G. Makin, and P. N. Sabes, “Nonhuman primate reaching with multichannel sensorimotor cortex electrophysiology,” May 2017. [Online]. Available: https://doi.org/10.5281/zenodo.788569

    work page doi:10.5281/zenodo.788569 2017

  18. [18]

    Optimizing the Automatic Selection of Spike Detection Thresholds Using a Multiple of the Noise Level,

    M. Rizk and P. D. Wolf, “Optimizing the Automatic Selection of Spike Detection Thresholds Using a Multiple of the Noise Level,”Medical & biological engineering & computing, vol. 47, no. 9, pp. 955–966, Sep. 2009

    work page 2009

  19. [19]

    An elec- tronic neuromorphic system for real-time detection of high frequency os- cillations (HFO) in intracranial EEG,

    M. Sharifshazileh, K. Burelo, J. Sarnthein, and G. Indiveri, “An elec- tronic neuromorphic system for real-time detection of high frequency os- cillations (HFO) in intracranial EEG,”Nature Communications, vol. 12, p. 3095, May 2021

    work page 2021

  20. [20]

    A 0.11–0.38 pj/cycle differential ring oscillator in 65 nm cmos for robust neurocomputing,

    X. Zhang, J. Acharya, and A. Basu, “A 0.11–0.38 pj/cycle differential ring oscillator in 65 nm cmos for robust neurocomputing,”IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 2, pp. 617–630, 2021

    work page 2021

  21. [21]

    A 10-bit charge-redistribution adc consum- ing 1.9µw at 1 ms/s,

    M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. A. M. Klumperink, and B. Nauta, “A 10-bit charge-redistribution adc consum- ing 1.9µw at 1 ms/s,”IEEE Journal of Solid-State Circuits, vol. 45, no. 5, pp. 1007–1015, 2010

    work page 2010

  22. [22]

    An Energy-Efficient Hybrid SAR-VCO\Delta \Sigma Capacitance-to-Digital Converter in 40-nm CMOS,

    A. Sanyal and N. Sun, “An Energy-Efficient Hybrid SAR-VCO\Delta \Sigma Capacitance-to-Digital Converter in 40-nm CMOS,”IEEE Jour- nal of Solid-State Circuits, vol. 52, no. 7, pp. 1966–1976, Jul. 2017

    work page 1966

  23. [23]

    Wireless neural recording with single low-power integrated circuit,

    R. R. Harrison, R. J. Kier, C. A. Chestek, V . Gilja, P. Nuyujukian, S. Ryu, B. Greger, F. Solzbacher, and K. V . Shenoy, “Wireless neural recording with single low-power integrated circuit,”IEEE Transactions on Neural Systems and Rehabilitation Engineering, vol. 17, no. 4, pp. 322–329, 2009

    work page 2009

  24. [24]

    Neuromorphic noise shaping in coupled neuron populations,

    J. Marienborg, T. Lande, and M. Hovin, “Neuromorphic noise shaping in coupled neuron populations,” in2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353), vol. 5, 2002, pp. V–V

    work page 2002