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arxiv: 2604.10093 · v1 · submitted 2026-04-11 · 💻 cs.AR

Late Breaking Results: CHESSY: Coupled Hybrid Emulation with SystemC-FPGA Synchronization

Lorenzo Ruotolo , Giovanni Pollo , Mohamed Amine Hamdi , Matteo Risso , Yukai Chen , Enrico Macii , Massimo Poncino , Sara Vinco
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Alessio Burrello Daniele Jahier Pagliari
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Pith reviewed 2026-05-10 16:03 UTC · model grok-4.3

classification 💻 cs.AR
keywords hybrid emulationSystemCFPGA co-emulationvirtual platformsRISC-Vopen-sourcecyber-physical systemsJTAG synchronization
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The pith

An open-source framework synchronizes SystemC virtual platforms with FPGA hardware to enable accurate full-system co-emulation.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper presents CHESSY, an open-source framework that couples SystemC-based virtual platforms with FPGA emulation for hybrid co-simulation of cyber-physical systems. The FPGA runs the core digital subsystems for speed and timing accuracy, while the virtual platform handles peripherals and non-digital elements. A wrapper manages synchronization over JTAG. On a RISC-V SoC example from biosignals processing, the setup delivers up to 2500 times faster execution than RTL simulation yet keeps overall runtime below twice that of pure FPGA emulation.

Core claim

CHESSY connects SystemC virtual platforms to FPGA emulation through a JTAG-based wrapper that coordinates timing and data exchange. This lets designers accelerate the main digital components on hardware while retaining flexible simulation of the rest of the system, producing up to 2500x speedup over RTL simulation and less than 2x the runtime of standalone FPGA emulation on the evaluated RISC-V SoC.

What carries the argument

The JTAG-based wrapper that coordinates timing and communication between the FPGA emulation and the SystemC virtual platform.

If this is right

  • Designers gain an open, vendor-independent path to hybrid emulation instead of relying on proprietary tools.
  • Full-system validation of cyber-physical designs can combine hardware-accurate digital timing with simulated non-digital components.
  • RISC-V based SoCs become practical to evaluate at scale with both speed and accuracy for embedded applications.
  • The same synchronization approach could support additional peripheral models without rewriting the FPGA design.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Alternative communication links such as PCIe could be tested to lower synchronization cost further.
  • The framework might extend to other simulation languages or mixed-signal domains not covered in the RISC-V example.
  • Larger IoT or automotive systems could use the same pattern to balance accuracy and simulation speed.

Load-bearing premise

The JTAG wrapper can keep the FPGA and SystemC sides synchronized without adding enough delay or error to erase the reported speed gains in practical full-system runs.

What would settle it

Measure wall-clock time for the RISC-V SoC biosignals workload under CHESSY, pure RTL simulation, and pure FPGA emulation to check whether the 2500x speedup versus RTL and the sub-2x overhead versus pure FPGA actually appear.

Figures

Figures reproduced from arXiv: 2604.10093 by Alessio Burrello, Daniele Jahier Pagliari, Enrico Macii, Giovanni Pollo, Lorenzo Ruotolo, Massimo Poncino, Matteo Risso, Mohamed Amine Hamdi, Sara Vinco, Yukai Chen.

Figure 1
Figure 1. Figure 1: Overview of CHESSY. The background shades in the pseudocode [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Simulation time overhead [%] for different transfer sizes and interaction [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
read the original abstract

The growing complexity of cyber-physical systems (CPSs) calls for early prototyping tools that combine accuracy, speed, and usability. Virtual Platforms (VPs) provide fast functional simulation, but hybrid co-emulation solutions, in which key digital components are deployed on FPGA, become necessary when accurate timing modelling is required and RTL simulation is too costly. However, existing hybrid emulation tools are mostly proprietary, and rely on vendor-specific FPGA features. To address this gap, we introduce an open-source framework that connects SystemC-based VPs with FPGA emulation, enabling full-system co-emulation of digital and non-digital components. The FPGA accelerates the execution of main digital subsystems, while a wrapper coordinates timing and communication with the VP through JTAG, maintaining synchronization with simulated peripherals. Evaluations using a RISC-V SoC, with an example in the biosignals processing domain, show up to 2500x speedup compared to RTL simulation, while maintaining less than 2x total simulation time relative to pure FPGA emulation.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The paper introduces CHESSY, an open-source framework for coupled hybrid emulation that connects SystemC-based virtual platforms with FPGA emulation through a JTAG wrapper for synchronization. It enables full-system co-emulation of digital and non-digital components in cyber-physical systems. Evaluations on a RISC-V SoC for biosignal processing demonstrate up to 2500x speedup over RTL simulation and less than 2x the simulation time of pure FPGA emulation.

Significance. If the synchronization and performance claims hold under detailed scrutiny, this open-source framework could provide a practical tool for early prototyping of complex cyber-physical systems, combining FPGA speed for digital cores with SystemC flexibility for peripherals and addressing the limitations of proprietary or slow RTL-only approaches. The open-source release is a clear strength for reproducibility and adoption.

major comments (2)
  1. [Abstract] Abstract: The headline performance claims (up to 2500x speedup vs. RTL simulation and <2x total time vs. pure FPGA emulation) are stated without any description of the experimental setup, workloads, RISC-V SoC configuration details, measurement methodology, baselines, error bars, or variability. This absence prevents verification of the results.
  2. [Framework description] JTAG wrapper and synchronization: The wrapper is said to 'coordinate timing and communication' and 'maintain synchronization,' but no quantitative bounds are given on round-trip JTAG latency, maximum sustainable event rate, or measured timing error versus a pure-FPGA baseline. These data are load-bearing for the <2x overhead claim, especially under full-system peripheral loads in biosignal processing.
minor comments (1)
  1. [Title] The manuscript is presented as 'Late Breaking Results,' which may suit a conference format but leaves the evaluation section unusually brief for a journal submission; expanding the experimental reporting would strengthen it.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the detailed and constructive review. The comments highlight opportunities to strengthen the clarity and verifiability of our results. We address each major comment below and will incorporate revisions in the next version of the manuscript.

read point-by-point responses

  1. Referee: [Abstract] Abstract: The headline performance claims (up to 2500x speedup vs. RTL simulation and <2x total time vs. pure FPGA emulation) are stated without any description of the experimental setup, workloads, RISC-V SoC configuration details, measurement methodology, baselines, error bars, or variability. This absence prevents verification of the results.

    Authors: We agree that the abstract, due to its brevity, does not include the requested experimental details. The full manuscript provides these in Section IV (Evaluation), including the RISC-V SoC configuration (RV32IMAC core with peripherals), the biosignal processing workload, cycle-accurate measurement methodology on the FPGA, baselines (RTL simulation via Verilator and pure FPGA emulation), and reported speedups. To improve standalone readability of the abstract, we will revise it to include a concise sentence summarizing the key setup parameters, workload, and measurement approach while respecting length constraints. We will also ensure error bars and variability data from repeated runs are explicitly reported in the evaluation section if not already detailed. revision: yes

  2. Referee: [Framework description] JTAG wrapper and synchronization: The wrapper is said to 'coordinate timing and communication' and 'maintain synchronization,' but no quantitative bounds are given on round-trip JTAG latency, maximum sustainable event rate, or measured timing error versus a pure-FPGA baseline. These data are load-bearing for the <2x overhead claim, especially under full-system peripheral loads in biosignal processing.

    Authors: The JTAG wrapper implementation and synchronization protocol are detailed in Section III, including the use of a custom protocol over the JTAG interface for event-driven communication. We acknowledge that explicit quantitative characterization of round-trip latency, sustainable event rate, and timing error relative to pure FPGA execution would provide stronger support for the overhead claims. We will add these measurements in the revised manuscript, obtained from targeted micro-benchmarks under varying peripheral loads representative of the biosignal processing application, to directly substantiate the <2x total time claim. revision: yes

Circularity Check

0 steps flagged

No circularity: empirical tool paper with measured timings only

full rationale

The paper describes an open-source hybrid SystemC-FPGA emulation framework and reports direct experimental results (up to 2500x speedup vs RTL, <2x overhead vs pure FPGA) from evaluations on a RISC-V SoC. No mathematical derivations, equations, parameter fitting, predictions, or first-principles claims exist that could reduce to inputs by construction. Synchronization is implemented via a JTAG wrapper whose behavior is described functionally; performance numbers are measured outcomes, not self-referential or fitted quantities presented as predictions. No self-citation chains or uniqueness theorems are invoked. This is a standard engineering tool paper whose central claims rest on external benchmarks and measurements, not internal circular logic.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

The paper is an engineering tool contribution with no explicit mathematical axioms, free parameters, or invented physical entities; the framework itself is the main addition.

pith-pipeline@v0.9.0 · 5513 in / 1163 out tokens · 64107 ms · 2026-05-10T16:03:44.131512+00:00 · methodology

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