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arxiv: 2604.19275 · v2 · pith:3VWLVCW5new · submitted 2026-04-21 · 📡 eess.SY · cs.OS· cs.RO· cs.SY

Scheduling Analysis of UAV Flight Control Workloads on PREEMPT_RT Linux Using a Raspberry Pi 5

Luiz Giacomossi , H{\aa}kan Forsberg , Ivan Tomasic , Baran \c{C}\"ur\"ukl\"u , Tommaso Cucinotta This is my paper

Pith reviewed 2026-05-10 02:09 UTC · model grok-4.3

classification 📡 eess.SY cs.OScs.ROcs.SY
keywords real-time LinuxPREEMPT_RTUAV flight controlRaspberry Pi 5scheduling latencymulti-core SoCmemory contentionSoftIRQ
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The pith

PREEMPT_RT Linux reduces worst-case latency for 250 Hz UAV control from over 9 ms to under 225 microseconds on Raspberry Pi 5.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper tests whether the PREEMPT_RT patch set can make a standard Linux kernel reliable enough to run both high-level autonomy and low-level flight control on the same multi-core chip inside a UAV. It measures a 250 Hz control loop under heavy stress on a Raspberry Pi 5 and compares the standard kernel to the real-time version. The real-time kernel cuts the longest observed delay by nearly 88 percent by forcing a direct wake-up path that avoids deferred kernel work. This matters because modern UAV designs want to eliminate separate microcontrollers for the safety-critical loops. The work shows that once operating-system noise is removed, the remaining timing variation comes from shared hardware resources on the chip.

Core claim

The analysis shows that the standard Linux kernel on Raspberry Pi 5 produces worst-case latencies exceeding 9 ms for a 250 Hz control loop under heavy stress, rendering it unsuitable for UAV flight control. In contrast, the PREEMPT_RT kernel reduces this latency by nearly 88 percent to under 225 microseconds by enforcing a direct wake-up path that bypasses SoftIRQ deferred execution and mitigates OS noise. The paper concludes that while PREEMPT_RT resolves scheduling variance, the residual jitter on modern multi-core SoCs is primarily driven by hardware memory contention.

What carries the argument

PREEMPT_RT's direct kernel-thread wake-up path that avoids SoftIRQ deferred execution, used to isolate hardware memory contention as the remaining source of jitter.

Load-bearing premise

The chosen heavy stress workloads and latency measurement approach on the Raspberry Pi 5 accurately represent real UAV flight control conditions and isolate the claimed causes without unaccounted hardware or software confounders.

What would settle it

Repeated measurements of the 250 Hz loop on the Raspberry Pi 5 with PREEMPT_RT that show worst-case latencies consistently above 225 microseconds under the heavy stress workloads would falsify the reported reduction and the attribution to hardware contention.

Figures

Figures reproduced from arXiv: 2604.19275 by Baran \c{C}\"ur\"ukl\"u, H{\aa}kan Forsberg, Ivan Tomasic, Luiz Giacomossi, Tommaso Cucinotta.

Figure 1
Figure 1. Figure 1: The outer loop features a Position Controller, which takes the position reference rr, the current position r, and the current linear velocity v as inputs. It calculates the total desired force vector F, required to track the position reference. Control Allocator Position Controller Attitude Controller F rr ψr r , v α , ωb τr ωi ∀i ∈ {1, 2, 3, 4} UAV [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Box plots comparing scheduling latency on the [PITH_FULL_IMAGE:figures/full_fig_p005_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Time-series latency under SCHED_OTHER on the standard kernel: standard priority (nice 0, top) and high pri￾ority (nice -19, bottom). The plots show increased latency and jitter under system stress (red) compared to the idle state (blue). 0 2000 4000 6000 8000 10000 Iteration 5 10 25 50 100 1000 L a t e n c y ( 7 s ) Latency for Scheduler: SCHED RR p50 Stress No Stress 0 2000 4000 6000 8000 10000 Iteration … view at source ↗
Figure 6
Figure 6. Figure 6: Time-series latency for SCHED_DEADLINE on the standard kernel, 400 µs runtime (top) versus 800 µs (bottom). Even with this reservation-based scheduler, there are significant latency spikes under stress (red). The traces reveal a contrast in the wake-up mechanism. The PREEMPT_RT kernel allows the hardware timer interrupt to wake the user task directly, resulting in a wake-up latency of just 7 µs. In contras… view at source ↗
Figure 7
Figure 7. Figure 7: Time-series latency for SCHED_RR on the PREEMPT_RT kernel, priority 50 (top) and 99 (bottom). In contrast to the standard kernel, the latency remains tightly bounded with minimal outliers, even when subjected to heavy system stress (red). 0 2000 4000 6000 8000 10000 Iteration 5 10 25 50 100 L a t e n c y ( 7 s ) Latency for Scheduler: SCHED FIFO p50 Stress No Stress 0 2000 4000 6000 8000 10000 Iteration 5 … view at source ↗
Figure 8
Figure 8. Figure 8: Latency for SCHED_FIFO on the PREEMPT_RT kernel for priorities 50 (top) and 99 (bottom). It shows a reduction in the magnitude of outliers under stress (red), demonstrating the improved effectiveness of the real-time kernel’s preemption model. The traces also revealed a secondary effect: the computa￾tional execution time of the control algorithm itself (ex￾cluding scheduling delay) increased from ≈ 3.8 µs … view at source ↗
read the original abstract

Modern UAV architectures increasingly aim to unify high-level autonomy and low-level flight control on a single General-Purpose Operating System (GPOS). However, complex multi-core System-on-Chips (SoCs) introduce significant timing indeterminism due to shared resource contention. This paper performs an architectural analysis of the PREEMPT RT Linux kernel on a Raspberry Pi 5, specifically isolating the impact of kernel activation paths (deferred execution SoftIRQs versus real-time direct activation) on a 250 Hz control loop. Results show that under heavy stress, the standard kernel is unsuitable, exhibiting worst-case latencies exceeding 9 ms. In contrast, PREEMPT RT reduced the worst-case latency by nearly 88 percent to under 225 microseconds, enforcing a direct wake-up path that mitigates OS noise. These findings demonstrate that while PREEMPT RT resolves scheduling variance, the residual jitter on modern SoCs is primarily driven by hardware memory contention.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The paper analyzes scheduling performance of the PREEMPT_RT Linux kernel versus the standard kernel on a Raspberry Pi 5 for 250 Hz UAV flight control workloads. Under heavy stress, it reports that the standard kernel exhibits worst-case latencies exceeding 9 ms while PREEMPT_RT reduces this by nearly 88% to under 225 μs via direct wake-up paths that mitigate OS noise; the residual jitter is attributed primarily to hardware memory contention on modern SoCs.

Significance. If the measurements hold, the results would offer practical value for real-time embedded control on multi-core SoCs, showing that PREEMPT_RT can make GPOS viable for UAV flight loops but that hardware contention remains the limiting factor. The direct empirical approach (latency traces under stress) is a strength as it supplies concrete, falsifiable numbers rather than fitted models.

major comments (2)
  1. [Abstract] Abstract: the central quantitative claims (88% reduction, 225 μs bound, 9 ms baseline) are stated without any accompanying description of measurement methodology, number of trials, data exclusion rules, timing source, or how the 250 Hz loop and stress workloads were implemented. This prevents verification of the performance numbers that support the entire contribution.
  2. [Abstract] Abstract and concluding discussion: the claim that 'residual jitter on modern SoCs is primarily driven by hardware memory contention' is presented as a finding, yet the manuscript supplies no differential experiments (cache partitioning, DRAM bandwidth saturation versus CPU-only stress, or hardware performance counter data) that isolate memory contention from other SoC factors such as interconnect contention, DMA, or thermal throttling.
minor comments (1)
  1. [Abstract] The abstract refers to 'heavy stress workloads' without specifying their composition or intensity; a brief table or paragraph in the experimental section would improve reproducibility.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive and detailed comments. We address each major comment point-by-point below, indicating planned revisions to the manuscript where appropriate.

read point-by-point responses

  1. Referee: [Abstract] Abstract: the central quantitative claims (88% reduction, 225 μs bound, 9 ms baseline) are stated without any accompanying description of measurement methodology, number of trials, data exclusion rules, timing source, or how the 250 Hz loop and stress workloads were implemented. This prevents verification of the performance numbers that support the entire contribution.

    Authors: The full experimental methodology—including latency measurement via cyclictest with CLOCK_MONOTONIC, the 250 Hz periodic task implementation, stress workloads (stress-ng for CPU/memory/I/O contention), sample count (>10^6 iterations), and worst-case analysis—is detailed in Sections 3 (Experimental Setup) and 4 (Results). To make the abstract more self-contained and address verification concerns, we will add a concise clause describing the measurement approach and stress conditions. revision: yes

  2. Referee: [Abstract] Abstract and concluding discussion: the claim that 'residual jitter on modern SoCs is primarily driven by hardware memory contention' is presented as a finding, yet the manuscript supplies no differential experiments (cache partitioning, DRAM bandwidth saturation versus CPU-only stress, or hardware performance counter data) that isolate memory contention from other SoC factors such as interconnect contention, DMA, or thermal throttling.

    Authors: We agree the manuscript lacks dedicated isolation experiments. The attribution is an inference drawn from the elimination of OS noise by PREEMPT_RT (leaving variability correlated with memory stress) plus known Raspberry Pi 5 SoC characteristics. We will revise the abstract and discussion to present this as a hypothesized primary source supported by the results and literature, rather than a definitively isolated conclusion, and note it as an avenue for future work involving performance counters. revision: partial

Circularity Check

0 steps flagged

No circularity: purely empirical latency measurements

full rationale

The paper reports direct experimental results from running 250 Hz control loops and heavy stress workloads on Raspberry Pi 5 hardware under standard and PREEMPT_RT kernels. No equations, derivations, fitted parameters, or predictions appear in the provided text or abstract; claims about latency reduction (88% to <225 µs) and residual jitter sources are inferences from measured traces rather than any self-referential reduction or self-citation chain. The analysis is self-contained against external benchmarks.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The central claim rests entirely on experimental observations under unspecified stress conditions; no free parameters, mathematical axioms, or invented entities are introduced.

axioms (1)
  • domain assumption The applied stress workloads and latency measurement method on Raspberry Pi 5 accurately reflect UAV flight control timing requirements and isolate OS versus hardware effects.
    Invoked implicitly to interpret the 88% improvement and residual jitter attribution.

pith-pipeline@v0.9.0 · 5493 in / 1226 out tokens · 34230 ms · 2026-05-10T02:09:52.268081+00:00 · methodology

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