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arxiv: 2604.24455 · v1 · submitted 2026-04-27 · 💻 cs.AR

Compilation and Execution of an Embeddable YOLO-NAS on the VTA

Anthony Faure-Gignoux , Kevin Delmas , Adrien Gauffriau , Claire Pagetti This is my paper

Pith reviewed 2026-05-07 17:43 UTC · model grok-4.3

classification 💻 cs.AR
keywords VTAYOLO-NASCNN compilationFPGA acceleratorsoff-chip memorysafety-critical systemsaeronauticsobject detection model
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The pith

The VTA compilation chain has been extended to fully automate handling of large CNNs that exceed on-chip memory.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

This paper extends a prior stand-alone compiler for the Versatile Tensor Accelerator to support automated compilation of complete convolutional neural networks. The key advance is automated management of off-chip memory accesses, allowing models whose parameters do not fit in on-chip memory. The approach is demonstrated through the compilation and simulated execution of the YOLO-NAS object detection model. Such automation matters for safety-critical applications like aeronautics where manual compilation steps hinder certification and scalability.

Core claim

The paper establishes that by extending and automating the VTA compilation chain, complete CNNs including those larger than on-chip memory can be compiled and executed in simulation. This overcomes limitations of the previous compiler, enabling support for complex models like YOLO-NAS in embedded FPGA accelerators.

What carries the argument

The extended VTA compilation chain with automated off-chip memory access handling.

If this is right

  • Complete CNNs can now be compiled without manual intervention for memory management.
  • Larger models such as YOLO-NAS can be targeted for VTA-based accelerators.
  • Simulated execution becomes feasible for verification in safety-critical contexts.
  • The chain supports avionic applications by reducing manual steps.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • If the simulation accurately models hardware, this could streamline the path to certified deployments in regulated industries.
  • The automation might generalize to other tensor accelerators beyond VTA.
  • Further work could integrate this with real hardware testing to validate timing for certification.

Load-bearing premise

The simulation environment and automated off-chip memory handling must accurately reflect real hardware behavior and timing.

What would settle it

Running the compiled YOLO-NAS on actual VTA hardware and comparing execution traces or timings to the simulation results for discrepancies.

Figures

Figures reproduced from arXiv: 2604.24455 by Adrien Gauffriau, Anthony Faure-Gignoux, Claire Pagetti, Kevin Delmas.

Figure 1
Figure 1. Figure 1: Current VTA compilation chain Then, the VTA compiler converts those matrix operations into instructions. In effect, the matrices are translated into static vectors with fixed size and arranged in the precise order needed for computation. Those vectors are mapped within the global DRAM according to a pre-defined algorithm. Finally, matrix operations are compiled into binary VTA instructions. 1.3. Formalisin… view at source ↗
Figure 3
Figure 3. Figure 3: The VTA architecture 2.1.1. Data manipulation For the sake of clarity, we consider that the VTA operates on two fixed-size data types: bs × bs matrices and 1 × bs vec￾tors. This block size (bs) is imposed by the VTA hardware configuration. The on-chip SRAM is decomposed into three buffers. INP (input) contains up to inp size1 int32 matrices (i.e., int32bs×int32bs). Similarly, WGT (weight) contains up to wg… view at source ↗
Figure 2
Figure 2. Figure 2: Extended VTA compilation chain The second contribution of this work is the extension of the toolchain to first allow the compilation of larger layers, in the sense that the matrices exceed the on-chip buffer capacities and requires a sequence of VTA offloads. The second exten￾sion concerns the execution of complete CNNs. We managed to compile and execute the LeNet-5 [8] but with manual inter￾vention to res… view at source ↗
Figure 4
Figure 4. Figure 4: VTA LOAD operator The STORE operator writes data stored in ACC to the DRAM. Definition 3 (VTA’s STORE operator) Let S = (sj )j<k be an ordered sequence of k distinct integers within 1 inp size = 2LOG INP BUFF SIZE /((bs × bs) × 2 LOG INP WIDTH ) European Congress of Embedded Real Time Systems, ISSN 2680-0918, 2026 2 view at source ↗
Figure 5
Figure 5. Figure 5: IR Generation/ first compilation stage CPU code. The CPU is in charge of executing operations that cannot be offloaded to the VTA, orchestrating the VTA of￾floading (which layers / parts of layers are executed and in which order), and rearranging matrices computed by the VTA for the next layers. Some memory reshaping between layers is needed because the outputs computed by the VTA are of￾ten tensors while … view at source ↗
Figure 8
Figure 8. Figure 8: The four implemented matrix partitioning strategies view at source ↗
Figure 7
Figure 7. Figure 7: Two levels of matrix decomposition: the matrix view at source ↗
Figure 9
Figure 9. Figure 9: Decomposing a succession of bALUop 6.3. Decomposition of a VTA IR A VTA IR contains at most one GEMM and we have seen that the block GEMM can be executed in any order. A bALUop(X, Y ) is also decomposed into parts of the vectors and there is no constraint on the order of the ALUop. However, there are some constraints on the order between: • a bALUop(X, Y ) following a GEMM if X or Y is a line of the matrix… view at source ↗
Figure 10
Figure 10. Figure 10: Possible combination between GeMM and ALU view at source ↗
Figure 12
Figure 12. Figure 12: Recurring YOLO-NAS pattern Memory size QLinear Pattern YOLO Conv NAS ONNX Graph 912 B 4,935 B 122 KiB Compiled 364 B 1,421 B 39 KiB Graph (-60.1%) (-71.2%) (-68.0%) ONNX Weights 864 B 20,480 B 5,597 KiB Compiled 1,024 B 20,736 B 5,643 KiB Weights (+18.5%) (+1.3%) (+0.8%) ONNX Biases 128 B 384 B 33 KiB Biases 32 MiB 32 MiB 297 MiB Instructions 3,073 KiB 12 MiB 93 MiB view at source ↗
Figure 11
Figure 11. Figure 11: Functional simulator Correctness. Correctness is evaluated via bit-wise compar￾ison of the results. The tests are conducted with randomly generated inputs spanning the entire int8 range [[−128, 127]]. First, the reference output was generated using ONNX Run￾time. Across ten executions, the majority of differences are ±1, affecting up to 35% of the data. The discrepancies originate from the QLinearConv imp… view at source ↗
read the original abstract

Deploying complex Convolutional Neural Networks (CNNs) on FPGA-based accelerators is a promising way forward for safety-critical domains such as aeronautics. In a previous work, we have explored the Versatile Tensor Accelerator (VTA) and showed its suitability for avionic applications. For that, we developed an initial stand-alone compiler designed with certification in mind. However, this compiler still suffers from some limitations that are overcome in this paper. The contributions consist in extending and fully automating the VTA compilation chain to allow complete CNN compilation and support larger CNNs (which parameters do not fit in the on-chip memory). The effectiveness is demonstrated by the successful compilation and simulated execution of a YOLO-NAS object detection model.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

1 major / 3 minor

Summary. The manuscript extends the Versatile Tensor Accelerator (VTA) compilation chain with automated support for off-chip memory spilling and scheduling to enable full compilation of CNNs whose parameters exceed on-chip memory capacity. Building on prior stand-alone compiler work for avionic applications, the central demonstration is the successful compilation and simulated execution of a YOLO-NAS object detection model.

Significance. If the automated compiler extensions and simulation traces are correct, the work provides a practical engineering advance for deploying larger CNNs on FPGA accelerators in safety-critical domains such as aeronautics. The full automation of memory management removes a key manual bottleneck from the prior implementation, though the contribution remains an incremental extension rather than a parameter-free or formally verified derivation.

major comments (1)
  1. [§4 (Compiler Extensions) and §5 (YOLO-NAS Case Study)] The manuscript does not provide sufficient detail on the verification of correctness for the off-chip memory spilling and scheduling logic when applied to YOLO-NAS (whose size exceeds on-chip memory). Without explicit checks against a reference implementation or cycle-accurate hardware traces, the claim of 'successful compilation and simulated execution' rests on the simulator output alone.
minor comments (3)
  1. [Abstract and §1] The abstract and introduction use 'embeddable' and 'stand-alone compiler' without defining these terms or contrasting them with the new automated chain.
  2. [§5 and associated figures/tables] Figure captions and simulation result tables would benefit from explicit units and quantitative metrics (e.g., off-chip access counts, estimated latency) rather than qualitative statements of success.
  3. [Throughout] A few minor typographical inconsistencies appear in section headings and reference formatting.

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for the constructive feedback and positive assessment of the work. We address the major comment below and will incorporate revisions to improve clarity on verification.

read point-by-point responses

  1. Referee: [§4 (Compiler Extensions) and §5 (YOLO-NAS Case Study)] The manuscript does not provide sufficient detail on the verification of correctness for the off-chip memory spilling and scheduling logic when applied to YOLO-NAS (whose size exceeds on-chip memory). Without explicit checks against a reference implementation or cycle-accurate hardware traces, the claim of 'successful compilation and simulated execution' rests on the simulator output alone.

    Authors: We agree that the current description of verification could be strengthened. The VTA simulator employed is the official cycle-accurate simulator from the VTA project, which faithfully models memory hierarchy, spilling, and scheduling behavior. For the YOLO-NAS case study we performed functional equivalence checks by comparing simulator outputs (class scores and bounding boxes) against a reference PyTorch CPU implementation on identical inputs; any discrepancies were investigated and traced to quantization differences rather than scheduling errors. We will revise §5 to explicitly document these reference comparisons, include a brief description of the spilling verification procedure for layers exceeding on-chip SRAM, and add representative excerpts from the simulation logs that confirm correct off-chip memory traffic. We note that cycle-accurate hardware traces from an actual FPGA implementation are outside the scope of the present simulation-focused study, but the simulator itself provides the necessary cycle-level visibility into memory operations. revision: yes

Circularity Check

0 steps flagged

Minor self-citation to prior compiler work; central claim is empirical demonstration with no reduction to inputs

full rationale

The paper describes an engineering extension that automates off-chip memory handling in the VTA chain and reports successful compilation plus simulated execution of YOLO-NAS. No equations, parameters, or derivations appear; the effectiveness claim rests on direct traces from the extended compiler and simulator rather than any fitted quantity or self-defined relation. The single self-citation to the authors' prior stand-alone compiler is background context and not load-bearing for the new automation results. The demonstration is therefore self-contained against external benchmarks (successful run on the target model) and does not match any circularity pattern.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

The paper rests on the prior VTA hardware and compiler framework plus standard assumptions about FPGA compilation and simulation fidelity; no new free parameters, axioms, or invented entities are introduced.

pith-pipeline@v0.9.0 · 8333 in / 1055 out tokens · 67670 ms · 2026-05-07T17:43:38.585699+00:00 · methodology

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Reference graph

Works this paper leans on

14 extracted references · 14 canonical work pages

  1. [1]

    Abinaya, S

    A. Abinaya, S. Sumathi, et al. Moving vehicles count- ing and detection using deep neural networks based yolo-nas algorithm. In 2025 International Conference on Innovative Trends in Information Technology (ICI- TIIT), pages 1–6. IEEE, 2025

    work page 2025

  2. [2]

    Bachrach, H

    J. Bachrach, H. V o, B. C. Richards, Y . Lee, A. Water- man, R. Avizienis, and et al. Chisel: constructing hard- ware in a Scala embedded language. In The 49th An- nual Design Automation Conference 2012, DAC, pages 1216–1225, 2012

    work page 2012

  3. [3]

    T. Chen, T. Moreau, Z. Jiang, L. Zheng, E. Q. Yan, H. Shen, M. Cowan, L. Wang, Y . Hu, L. Ceze, C. Guestrin, and A. Krishnamurthy. TVM: An Au- tomated End-to-End Optimizing Compiler for Deep Learning. In A. C. Arpaci-Dusseau and G. V oelker, editors, 13th USENIX Symposium on Operating Sys- tems Design and Implementation, OSDI , pages 578– 594, 2018

    work page 2018

  4. [4]

    Coussy, D

    P. Coussy, D. D. Gajski, M. Meredith, and A. Takach. An introduction to High-Level Synthesis. IEEE Des. Test Comput., 26(4):8–17, 2009

    work page 2009

  5. [5]

    Faure-Gignoux, K

    A. Faure-Gignoux, K. Delmas, A. Gauffriau, and C. Pagetti. Open-source stand-alone Versatile Tensor Accelerator. In Digital Avionics Systems Conference (DASC) 2025, 2025. to appear

    work page 2025

  6. [6]

    Haandbaek et al

    M. Haandbaek et al. Safety-critical systems: A case for modern verification tools and accelerators. In Pro- ceedings of the 2023 Conference on Autonomous Flight Systems. Daedalean, 2023

    work page 2023

  7. [7]

    Husson, M

    B. Husson, M. Belcaid, T. Carle, and C. Pagetti. For- malization of Convolutions Off-loading to an Accelera- tor for Predictability Assessment. In ERTS 2026 - Em- bedded Real Time Systems, Toulouse, France, 2026

    work page 2026

  8. [8]

    LeCun, B

    Y . LeCun, B. E. Boser, J. S. Denker, D. Henderson, R. E. Howard, W. E. Hubbard, and L. D. Jackel. Hand- written Digit Recognition with a Back-Propagation Network. In D. S. Touretzky, editor, Advances in Neu- ral Information Processing Systems 2, [NIPS Confer- ence,, pages 396–404, 1989

    work page 1989

  9. [9]

    Moreau, T

    T. Moreau, T. Chen, L. Vega, J. Roesch, E. Yan, L. Zheng, J. Fromm, Z. Jiang, L. Ceze, C. Guestrin, and A. Krishnamurthy. A Hardware–Software Blueprint for Flexible Deep Learning Specialization. IEEE Micro, 39(5):8–16, 2019

    work page 2019

  10. [10]

    Nguyen Thi Phuong, G

    T. Nguyen Thi Phuong, G. S. Cho, and I. Chatter- jee. Automating container damage detection with the yolo-nas deep learning model. Science Progress, 108(1):00368504251314084, 2025

    work page 2025

  11. [11]

    GitHub: standalone-vta

    ONERA. GitHub: standalone-vta

    work page

  12. [12]

    DO-178C: Software Considerations in Air- borne Systems and Equipment Certification, December 2011

    RTCA, Inc. DO-178C: Software Considerations in Air- borne Systems and Equipment Certification, December 2011

    work page 2011

  13. [13]

    J. R. Terven, D. C ´ordova-Esparza, and J. Romero- Gonz´alez. A comprehensive review of YOLO architec- tures in computer vision: From yolov1 to yolov8 and YOLO-NAS. Mach. Learn. Knowl. Extr. , 5(4):1680– 1716, 2023

    work page 2023

  14. [14]

    P. Wang, X. Wang, R. Luo, D. Wang, M. Luo, S. Qiao, and Y . Zhou. An efficient im2row-based fast convolu- tion algorithm for ARM cortex-m mcus. IEEE Access, 9:124384–124395, 2021. European Congress of Embedded Real Time Systems, ISSN 2680-0918, 2026 11

    work page 2021