Integrated photonic computing: towards high-dimensional information processing

The rapid growth of artificial intelligence, coupled with the slowing of Moore's law, is straining computing infrastructure, as CMOS electronics face inherent limits in bandwidth, energy efficiency, and parallelism. Integrated photonic computing encodes and processes information using the phase, amplitude, spatial modes, wavelength channels, and polarisation of guided optical fields, offering a scalable and energy-efficient route beyond charge-based signalling. Here, we review on-chip photonic computing, emphasising the progression from low-dimensional to high-dimensional architectures. At the foundational level, low-dimensional approaches manipulate the phase and amplitude of guided light through Mach-Zehnder interferometers, diffractive structures, microring resonators, and absorptive elements, forming a programmable basis for optical matrix-vector multiplication. Crucially, high-dimensional architectures exploit spatial modes and wavelength channels to carry multiple independent data streams through a single waveguide, achieving higher throughput with moderate hardware overhead. Practical deployment, however, demands more than device innovation. We examine how system-level techniques, from time-wavelength interleaving to hardware-aware training, address energy efficiency, precision, and algorithm-hardware co-design. Five challenges nevertheless remain: electro-optic conversion efficiency, computing parallelism, spatial integration, reconfigurability, and robustness. We highlight emerging topological structures, such as optical skyrmions, as a promising route to fault-tolerant, topologically protected encoding that exploits the largely untapped polarisation degree of freedom. We argue that, by embracing the higher dimensionality of light, photonic computing can offer not merely an incremental improvement but a new paradigm for high-performance, energy-efficient information processing.