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arxiv: 2606.28705 · v1 · pith:I52XR4X7new · submitted 2026-06-27 · 📡 eess.SY · cs.SY

Negative Resistance Caused by Intra-Loop Coupling in Virtual-Admittance-Based Grid-Forming Control

Jaekeun Lee , Minwoo Jeong , Jae-Jung Jung , Xiongfei Wang , Shenghui Cui This is my paper

Pith reviewed 2026-06-30 09:20 UTC · model grok-4.3

classification 📡 eess.SY cs.SY
keywords virtual admittancegrid-forming controlnegative resistanceintra-loop couplingoutput impedanceharmonic instabilitydamping controlpassivity
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The pith

Intra-loop coupling among virtual-admittance control, current control, and voltage feedforward produces an s-squared term in inverter output impedance that creates negative resistance at harmonics independent of control delay.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper establishes that virtual-admittance-based grid-forming control harbors an instability source distinct from the well-known digital-delay effects. The coupling of the virtual-admittance outer loop with the inner current loop and voltage feedforward path inserts an s-squared term into the closed-loop output impedance. This term produces a negative real part in the impedance at harmonic frequencies. Because the term survives even when delay is removed, the resulting instability cannot be fixed by the usual delay-compensation techniques. The authors therefore introduce a passivity-oriented damping term that restores positive resistance while leaving the existing current controller and feedforward path unchanged.

Core claim

The intra-loop coupling among the VA control, the inner-loop current control, and the voltage feedforward control results in an s^2-term in the equivalent output impedance of the inverter, which induces a negative-resistance property in the harmonic range. This negative resistance is independent of the control delay. Consequently, this harmonic instability mechanism is fundamentally different from the extensively investigated cases in the literature, which are induced by the digital control delay of inverters. A simple passivity-oriented damping control is proposed to mitigate the negative resistance arising from the intra-loop coupling without requiring grid impedance information.

What carries the argument

The equivalent output impedance obtained from small-signal modeling of the three coupled loops, whose s-squared term supplies the negative real part at harmonic frequencies.

If this is right

  • The negative-resistance region remains even if control delay is eliminated, so conventional delay-mitigation methods cannot remove this instability source.
  • The proposed damping controller restores passivity while preserving the original current loop and voltage feedforward structure.
  • Stability analysis based solely on delay-induced negative resistance will miss this mechanism in VA-based grid-forming inverters.
  • The damping solution does not require knowledge of grid impedance, allowing deployment without additional measurements.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Similar intra-loop coupling may exist in other multi-loop converter controls that combine admittance shaping with inner current regulation and feedforward paths.
  • The s-squared term could interact with grid resonances at specific harmonic frequencies, producing localized instability that only appears under certain grid conditions.
  • Extending the impedance model to include PWM and sensor dynamics would test whether the negative-resistance prediction survives those additional lags.

Load-bearing premise

The small-signal model that yields the equivalent output impedance fully represents the closed-loop dynamics without unmodeled contributions from PWM or sensor dynamics.

What would settle it

An experimental frequency-response measurement of the inverter output impedance that shows no negative real part in the harmonic band when control delay is removed or compensated would falsify the claim that the intra-loop coupling produces delay-independent negative resistance.

Figures

Figures reproduced from arXiv: 2606.28705 by Jae-Jung Jung, Jaekeun Lee, Minwoo Jeong, Shenghui Cui, Xiongfei Wang.

Figure 1
Figure 1. Figure 1: (a) Control diagram VA-CC, composed of VA, CC, and VFF. (b) [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗
Figure 3
Figure 3. Figure 3: Negative-resistance caused by intra-loop coupling within VA-CC: (a) [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Real part of Zeq,0(jω) in the frequency range up to 300 Hz, (a) under different fcc and fixed nXR = 5, (b) under different nXR and fixed fcc = 1000 Hz. The circle plots represent the simulation-scanned results. which result from the intra-loop coupling within VA-CC. Notice that the term s 2 appears explicitly in Zeq,0(s). This term arises from the product of two inductive terms, sLf and sLv, as demonstrate… view at source ↗
Figure 5
Figure 5. Figure 5: Impedance plots of Zeq,0(s) and Zg(s). (a) Plots of Zeq,0(s) and Zg(s), (b) magnified view from 400 to 800 Hz. The circle plots represent the simulation-scanned results. impedance plot shown in [PITH_FULL_IMAGE:figures/full_fig_p005_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Comparison of Zeq(s) and Zeq,0(s), together with the scanned results of the time-domain simulation, for different amounts of control delay Td. Control parameters are fcc = 1 kHz, Lv = 0.5 p.u., and nXR = 5. III. DETAILED ANALYSIS OF NEGATIVE-RESISTANCE PROPERTY IN INVERTERS WITH CONVENTIONAL VA-CC In physical implementation, a control delay is inevitable and must be considered in an elaborate manner. There… view at source ↗
Figure 7
Figure 7. Figure 7: Diagram of phase angle responses of each approximated factors. (a) [PITH_FULL_IMAGE:figures/full_fig_p007_7.png] view at source ↗
Figure 10
Figure 10. Figure 10: Comparison of Zeq(s) and two different Zg(s) for two different Cg: Cg = 6 µF (stable), Cg = 36 µF (unstable). region of the VA-CC-based inverter. However, when fLC,g becomes smaller, i.e., for Cg = 36 µF, fLC,g can fall below fD = 449.8 Hz, and the system can become unstable. In this case with fLC,g = 256.4 Hz, the grid-side LC resonance peak occurs in the frequency region where Zeq(s) exhibits the negati… view at source ↗
Figure 11
Figure 11. Figure 11: Diagram of proposed VA with PVR. The PVR effect is negligible [PITH_FULL_IMAGE:figures/full_fig_p009_11.png] view at source ↗
Figure 13
Figure 13. Figure 13: Range of Rv,p (shaded) that ensures a positive-real Z prop eq (s) up to 5 kHz, with Td = 75 µs. (a) Lv is fixed at 0.5 p.u. and fcc varies. (b) fcc is fixed at 1.5 kHz and Lv varies. Considering the control delay, Z prop eq (s) is expressed as Z prop eq (s) = − ∆v ∆i = Gd(s)Gcc(s) + sLf 1 − Gd(s) + Gd(s)Gcc(s)Y prop v (s) , (22) similar to (11), but using Y prop v (s) instead of Yv(s). The impedance plots… view at source ↗
Figure 12
Figure 12. Figure 12: Comparison of Zeq(s) and Z prop eq (s) for different PVRs, together with the scanned results of the time-domain simulation. (a) From 50 Hz to 10 kHz. (b) Magnified view of the phase plot in (a), from 50 Hz to 1 kHz. accurately hold at frequencies approaching the switching frequency, where switching effects, sampling, and discrete￾time phenomena become significant. Enforcing a positive-real condition in a … view at source ↗
Figure 14
Figure 14. Figure 14: Experimental verification of Subsection III-C. (a) Experimental results, from the conventional method (fcc = 600 Hz to fcc = 1.5 kHz) to the proposed method (fcc = 1.5 kHz). (b) FFT result of the conventional method, (c) FFT result of the proposed method. that Rcc v,p, determined by (21), keeps Z prop eq (s) positive-real within the investigated frequency range. Thus, (21) provides a practically valid app… view at source ↗
Figure 15
Figure 15. Figure 15: Experimental verification of Subsection III-D, with Cg = 36 µF. (a) Experimental results, from the proposed method to conventional method, then back to proposed method (fcc = 600 Hz). (b) FFT result of the conventional method, (b) FFT result of the proposed method. Conventional, fcc = 600 Hz Proposed, fcc = 600 Hz Proposed, fcc = 900 Hz Proposed, fcc = 1.2 kHz Proposed, fcc = 1.5 kHz 0 V 0 A Line-to-line … view at source ↗
Figure 16
Figure 16. Figure 16: Experimental verification of the proposed method under various CC bandwidths, under the grid condition of SCR [PITH_FULL_IMAGE:figures/full_fig_p012_16.png] view at source ↗
Figure 17
Figure 17. Figure 17: Experimental verification of the proposed method under various [PITH_FULL_IMAGE:figures/full_fig_p013_17.png] view at source ↗
read the original abstract

This paper addresses the harmonic instability problem of the virtual-admittance (VA)-based grid-forming control. It is revealed that the intra-loop coupling among the VA control, the inner-loop current control, and the voltage feedforward control results in an \(s^2\)-term in the equivalent output impedance of the inverter, which induces a negative-resistance property in the harmonic range. It is worth highlighting that this negative resistance is independent of the control delay. Consequently, this harmonic instability mechanism is fundamentally different from the extensively investigated cases in the literature, which are induced by the digital control delay of inverters. Then, a simple passivity-oriented damping control is proposed to mitigate the negative resistance arising from the intra-loop coupling. The method fully retains the well-established current controller and voltage feedforward, and does not require grid impedance information. Finally, experimental tests verify the theoretical findings and the effectiveness of the damping method.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The manuscript analyzes harmonic instability in virtual-admittance (VA)-based grid-forming inverter control. It shows that intra-loop coupling among the VA controller, inner current loop, and voltage feedforward path produces an s² term in the closed-loop output impedance Z_out(s). This term creates a negative-resistance region in the harmonic frequency band and is asserted to be independent of digital control delay, distinguishing it from delay-induced mechanisms in the literature. A passivity-oriented damping controller is introduced to restore positive resistance while preserving the existing current controller and voltage feedforward paths and without requiring grid-impedance knowledge. Experimental results are cited to confirm both the impedance behavior and the damping effectiveness.

Significance. If the modeling and experimental evidence hold, the work identifies a previously under-examined source of negative resistance that is intrinsic to the control architecture rather than to delay. The proposed damping method is practically attractive because it is local, retains standard inner-loop structures, and avoids grid-parameter dependence. This could inform stability-oriented design of grid-forming inverters operating near weak grids or with high harmonic content.

major comments (2)
  1. [Small-signal modeling (Z_out derivation)] Small-signal modeling section (derivation of Z_out(s)): the block-diagram reduction yielding the s² coefficient in the output impedance treats the PWM as an ideal gain and the voltage/current sensors as unity. The stress-test concern is load-bearing: realistic PWM delay and sensor filtering enter the loop before the feedforward path and can change the sign of the s² term or introduce dominating higher-order dynamics in the 250–750 Hz range. The manuscript must demonstrate that the claimed negative-resistance property and its delay independence survive these additions; otherwise the distinction from delay-induced mechanisms is not secured.
  2. [Impedance analysis] Impedance analysis (expression for Re{Z_out(jω)} in harmonic band): the claim that the negative resistance arises solely from intra-loop coupling and is independent of control delay rests on the specific form of the s² term. Without an explicit comparison of the full closed-loop transfer function with and without the PWM/sensor blocks, it remains unclear whether the sign of the real part is robust or an artifact of the ideal-gain assumption.
minor comments (2)
  1. [Experimental verification] The abstract states that experimental tests verify the findings, but the main text should include a brief description of the test setup (grid impedance, operating point, harmonic injection method) to allow readers to assess the generality of the results.
  2. [Control structure] Notation for the VA admittance and the damping gain should be introduced consistently when first appearing in the control diagram and in the impedance equations.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the careful review and for identifying the need to strengthen the modeling assumptions in our analysis of intra-loop coupling. The comments are well-taken and have prompted us to extend the small-signal model. We respond to each major comment below and indicate the corresponding revisions.

read point-by-point responses

  1. Referee: [Small-signal modeling (Z_out derivation)] Small-signal modeling section (derivation of Z_out(s)): the block-diagram reduction yielding the s² coefficient in the output impedance treats the PWM as an ideal gain and the voltage/current sensors as unity. The stress-test concern is load-bearing: realistic PWM delay and sensor filtering enter the loop before the feedforward path and can change the sign of the s² term or introduce dominating higher-order dynamics in the 250–750 Hz range. The manuscript must demonstrate that the claimed negative-resistance property and its delay independence survive these additions; otherwise the distinction from delay-induced mechanisms is not secured.

    Authors: We agree that the original derivation used ideal PWM gain and unity-gain sensors. The s² term, however, is generated by the algebraic summation of the virtual-admittance current reference, the inner current controller output, and the voltage feedforward term; these operations occur upstream of both the PWM and the sensor paths. To verify robustness we have augmented the model with a first-order Padé approximation of the computational/PWM delay and first-order sensor filters. The revised closed-loop Z_out(s) retains a negative leading s² coefficient whose sign is unchanged in the 250–750 Hz band. The updated Section III now contains the extended block diagram, the modified transfer-function derivation, and numerical evaluations confirming that the negative-resistance region survives. This preserves the claimed distinction from purely delay-induced mechanisms. revision: yes

  2. Referee: [Impedance analysis] Impedance analysis (expression for Re{Z_out(jω)} in harmonic band): the claim that the negative resistance arises solely from intra-loop coupling and is independent of control delay rests on the specific form of the s² term. Without an explicit comparison of the full closed-loop transfer function with and without the PWM/sensor blocks, it remains unclear whether the sign of the real part is robust or an artifact of the ideal-gain assumption.

    Authors: The referee correctly notes the absence of an explicit side-by-side comparison. In the revised manuscript we derive the full closed-loop output impedance both with and without the PWM delay (e^{-sT_d}) and sensor filters, then plot Re{Z_out(jω)} for both cases over the harmonic range. The negative-resistance interval remains present in both models, with only small boundary shifts attributable to the additional phase lag. The comparison is now included as a new figure and accompanying equations in Section IV, directly addressing the concern and reinforcing that the sign of the real part is attributable to the intra-loop coupling rather than the ideal-gain simplification. revision: yes

Circularity Check

0 steps flagged

Derivation of s^2 term and negative resistance from intra-loop coupling is self-contained

full rationale

The paper obtains the s^2 term in the equivalent output impedance by reducing the block diagram of the VA control, inner current loop, and voltage feedforward path. The abstract states this coupling 'results in an s^2-term ... which induces a negative-resistance property' and notes the result is 'independent of the control delay.' No fitted parameters are introduced to produce the sign of the real part, no self-citation chain is used to justify the model structure, and the derivation is not shown to be equivalent to its inputs by construction. Standard small-signal assumptions (ideal PWM, unity sensors) are explicit modeling choices rather than tautological redefinitions. This is the normal non-circular outcome for a control-theoretic impedance derivation.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The central claim rests on standard small-signal linearization of inverter control loops and the validity of the equivalent output impedance representation; no free parameters or invented entities are visible in the abstract.

axioms (1)
  • domain assumption Small-signal modeling of the VA control, current loop, and voltage feedforward accurately captures the closed-loop output impedance.
    Invoked to derive the s^2 term and negative-resistance property.

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