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arxiv: 2607.00841 · v1 · pith:3FWOQJGBnew · submitted 2026-07-01 · ⚛️ physics.ins-det

Real-Time FPGA-Based SiPM Detector Emulation Using a Temporally Quantized Model

Stefano Carsi , Edoardo Proserpio , Andrea Abba , Francesco Caponio , Valentina Arosio This is my paper

Pith reviewed 2026-07-02 03:19 UTC · model grok-4.3

classification ⚛️ physics.ins-det
keywords silicon photomultiplierFPGA emulationreal-time detector signalshardware-in-the-loop testingtemporal quantizationrecursive signal filtersanalog waveform generationphoton event processing
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The pith

An FPGA system converts photon event streams into real-time analog waveforms that match silicon photomultiplier detector output.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper shows how to build a hardware emulator that takes incoming photon detection events and turns them into continuous analog signals without storing or replaying fixed waveforms. Time is split into bins that match the device clock cycle, events inside each bin are summed, and a weighted average keeps timing detail inside the bin. Parallel recursive filters then build the rise and decay shape of the pulse before dual high-speed converters send the result to the analog output. This setup runs at full speed with low overhead and supports direct testing of readout electronics using live, variable inputs instead of static files. The same structure works for other detector types because the core steps stay independent of the specific sensor model.

Core claim

The system receives simulated photon events and performs on-chip temporal quantization by dividing time into bins equal to one clock cycle. Hits inside each bin are accumulated and combined with a weighted temporal averaging scheme that keeps sub-bin precision. Signal shaping runs entirely in hardware through parallel one-pole recursive filters that produce the rise and two decay components. The shaped waveform is sent through dual 16-bit digital-to-analog converters running at 2.5 gigasamples per second, producing physically accurate detector signals in real time.

What carries the argument

Temporally quantized model that bins photon events to clock cycles, applies weighted averaging inside each bin, and uses parallel one-pole recursive filters to shape the final waveform.

If this is right

  • The architecture supports hardware-in-the-loop testing of front-end electronics with live variable signals.
  • It achieves high throughput and low latency while keeping processor overhead minimal.
  • Inputs can arrive from a 10-gigabit Ethernet stream or directly from the on-chip processing system.
  • The same structure generalizes beyond silicon photomultipliers to other detector types.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • If the output fidelity holds under varied rates, labs could replace some physical detector setups during electronics development cycles.
  • The clock-bin approach might extend to real-time emulation tasks in other instrumentation fields where sub-cycle timing matters.
  • Direct comparison tests at extreme photon rates would show the practical limits of the averaging step.
  • The dual-converter output opens compatibility with existing high-speed analog test benches.

Load-bearing premise

The binning plus weighted averaging and recursive filters are assumed to keep timing and amplitude close enough to real detector output that front-end electronics respond the same way.

What would settle it

Feed identical photon input streams to both the emulator and a real silicon photomultiplier, then compare the digital output of the same front-end electronics to see whether the responses differ beyond measurement noise.

Figures

Figures reproduced from arXiv: 2607.00841 by Andrea Abba, Edoardo Proserpio, Francesco Caponio, Stefano Carsi, Valentina Arosio.

Figure 1
Figure 1. Figure 1: Functional architecture of the detector emulator. An amplitude [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Ideal SiPM response of (5), shown as the sum (solid) of its rise, fast [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Temporal quantization of a 20-photoelectron event. Top: individual photon hits with continuous-time timestamps as produced by the simulation. [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: System architecture and data path. Quantized [PITH_FULL_IMAGE:figures/full_fig_p004_4.png] view at source ↗
Figure 6
Figure 6. Figure 6: Look-ahead transformation. The naive IIR (top) has feedback distance [PITH_FULL_IMAGE:figures/full_fig_p005_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: Prototype board. The central heat sink covers the Zynq UltraScale+ [PITH_FULL_IMAGE:figures/full_fig_p005_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: Single-event validation for a 20-photoelectron event. Top: full waveform. Middle: zoom on the rising edge and peak. Bottom: relative error of the [PITH_FULL_IMAGE:figures/full_fig_p006_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: Pile-up validation. Three scintillation-like events of [PITH_FULL_IMAGE:figures/full_fig_p006_9.png] view at source ↗
read the original abstract

We present a real-time hardware implementation of a versatile detector emulator capable of reproducing realistic silicon photomultiplier signals. Our approach builds upon the open-source SimSiPM framework, originally developed to simulate the microscopic response of silicon photomultipliers, including photon detection efficiency, optical crosstalk, afterpulsing, and dark counts. SimSiPM provides idealized photon-level data with arbitrary temporal and amplitude resolution. In contrast, our emulator, built on a field-programmable gate array, translates this fine-grained simulation into physically realizable analog signals, maintaining real-time operation and finite hardware resolution. The system receives simulated photon events either via a 10-gigabit Ethernet stream or directly from the processing system of a system-on-chip, and performs on-chip temporal quantization, dividing time into bins equal to one clock cycle. All photon hits within a bin are accumulated, and their contribution is combined through a weighted temporal averaging scheme that preserves sub-bin precision. Signal shaping is executed entirely in hardware, using parallel one-pole recursive filters that synthesize the rise and the two decay components of the response. The resulting waveform is converted to analog through dual 16-bit digital-to-analog converters operating at 2.5 gigasamples per second. This architecture generates physically accurate detector signals in real time, rather than replaying precomputed waveforms. It also generalizes beyond silicon photomultipliers, providing a flexible framework for hardware-in-the-loop testing of front-end electronics. The proposed implementation demonstrates high throughput, low latency, and minimal processor overhead.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The manuscript presents an FPGA-based real-time emulator for SiPM detector signals. It ingests photon-level events from the SimSiPM framework (via 10 GbE or on-chip), performs clock-cycle temporal binning with weighted sub-bin averaging to preserve precision, applies parallel one-pole recursive filters to synthesize the rise plus two decay components, and drives dual 16-bit 2.5 GS/s DACs to produce analog waveforms. The central claim is that this architecture generates physically accurate detector signals in real time (rather than replaying precomputed waveforms) and provides a general framework for hardware-in-the-loop testing of front-end electronics.

Significance. A validated implementation would offer a useful capability for detector electronics testing by enabling flexible, low-latency, real-time analog signal generation without reliance on physical detectors or stored waveform libraries. The hardware description itself is a concrete contribution to the instrumentation literature, but its impact hinges on demonstrated fidelity.

major comments (2)
  1. [Abstract] Abstract: The claim that the architecture 'generates physically accurate detector signals in real time' is unsupported by any quantitative fidelity metrics. No RMS error, timing jitter, amplitude deviation, or side-by-side waveform comparisons against SimSiPM reference signals are reported to verify that the clock-cycle binning, weighted temporal averaging, and one-pole recursive filters preserve the required timing and amplitude fidelity.
  2. [FPGA pipeline / signal shaping] Architecture description (FPGA pipeline section): The assumption that the weighted temporal averaging scheme within each clock-cycle bin combined with the parallel one-pole filters 'preserves sub-bin precision' and produces signals 'indistinguishable from real SiPM output' for front-end testing is stated but not demonstrated. No error budgets, performance numbers, or validation against the high-resolution SimSiPM photon-level data are supplied, leaving the central accuracy assertion as an untested modeling assumption.
minor comments (1)
  1. The manuscript would benefit from explicit statements of the target clock frequency, filter coefficients, and DAC output scaling to allow reproduction.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive comments highlighting the need for quantitative validation. We agree that the current manuscript lacks explicit fidelity metrics and will revise to include them, strengthening the central claims without altering the described architecture.

read point-by-point responses

  1. Referee: [Abstract] Abstract: The claim that the architecture 'generates physically accurate detector signals in real time' is unsupported by any quantitative fidelity metrics. No RMS error, timing jitter, amplitude deviation, or side-by-side waveform comparisons against SimSiPM reference signals are reported to verify that the clock-cycle binning, weighted temporal averaging, and one-pole recursive filters preserve the required timing and amplitude fidelity.

    Authors: We acknowledge that the abstract claim is not yet supported by quantitative metrics in the submitted manuscript. The revised version will add RMS error, timing jitter, amplitude deviation statistics, and direct waveform overlays comparing the FPGA output against the high-resolution SimSiPM reference signals for representative photon clusters, thereby demonstrating that the binning and filter stages preserve the required fidelity. revision: yes

  2. Referee: [FPGA pipeline / signal shaping] Architecture description (FPGA pipeline section): The assumption that the weighted temporal averaging scheme within each clock-cycle bin combined with the parallel one-pole filters 'preserves sub-bin precision' and produces signals 'indistinguishable from real SiPM output' for front-end testing is stated but not demonstrated. No error budgets, performance numbers, or validation against the high-resolution SimSiPM photon-level data are supplied, leaving the central accuracy assertion as an untested modeling assumption.

    Authors: The manuscript currently presents the weighted averaging and parallel filter implementation as a design choice but does not supply the requested error budgets or validation plots. We will add a dedicated validation subsection containing quantitative error metrics (RMS, peak timing/amplitude deviation) and example waveform comparisons against SimSiPM, together with a brief error-budget analysis of the quantization and filter stages. revision: yes

Circularity Check

0 steps flagged

No circularity: hardware implementation description with independent content

full rationale

The manuscript describes an FPGA pipeline for real-time SiPM signal emulation based on external SimSiPM photon-level data. It specifies temporal binning, weighted averaging, and parallel one-pole recursive filters but contains no derivations, fitted parameters, or output quantities defined in terms of the claimed results. No self-citations are load-bearing for any uniqueness theorem or ansatz. The architecture is presented as a direct translation of input events to DAC output; the accuracy claim is an engineering assertion rather than a self-referential prediction. This is a standard non-circular implementation paper.

Axiom & Free-Parameter Ledger

0 free parameters · 2 axioms · 0 invented entities

The paper is an engineering implementation report. It relies on standard digital signal processing assumptions rather than new physical axioms or fitted parameters.

axioms (2)
  • domain assumption One-pole recursive filters can accurately synthesize the rise and dual-decay components of SiPM pulses when implemented in parallel hardware.
    Invoked in the signal-shaping section of the abstract.
  • domain assumption Weighted temporal averaging within clock-cycle bins preserves sub-bin timing precision sufficiently for realistic detector emulation.
    Central to the temporal quantization step described in the abstract.

pith-pipeline@v0.9.1-grok · 5821 in / 1385 out tokens · 45991 ms · 2026-07-02T03:19:07.267564+00:00 · methodology

discussion (0)

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Reference graph

Works this paper leans on

10 extracted references · 1 canonical work pages

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