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REVIEW 4 major objections 4 minor 84 references

MCHA: A Memory-Centric Hierarchical Architecture for Parallel-Sequential Computing

T0 review · 4 major / 4 minor · reviewed 2026-08-11 · deepseek-v4-flash

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Pith's one-line read The paper claims that replacing the centralized global memory of conventional accelerators with a hierarchical, peer-to-peer fabric of memory-centric cores eliminates the memory bottleneck for parallel-sequential workloads, yielding 153x…

desk verdict A credible and unusually complete memory-centric architecture paper whose headline MARL speedups are inflated by GPU JIT overhead, but the paper itself discloses this and the core design deserves serious refereeing. read the letter →

arxiv 2608.04443 v2 pith:6MSO2VJM submitted 2026-08-05 cs.AR cs.DCcs.MA

Daijing Shi , Hongxiao Zhao , Yihan Fu , Zhan Chen , Jiayi Li , Yihang Zhu , Anjunyi Fan , Yaoyu Tao
show 2 more authors
Yuchao Yang Bonan Yan
This is my paper · ORCID
classification cs.ARcs.DCcs.MA
keywords memory-centricarchitectureparallel-sequentialcomputingmulti-agentreinforcementlearningnetwork-on-chipdata-drivenprogrammingevent-driventriggerscycle-accuratesimulationbulksynchronousparallel
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The authors are trying to establish that a broad class of workloads they call parallel-sequential computing, including multi-agent reinforcement learning, spiking neural models, and bulk-synchronous graph algorithms, is throttled not by arithmetic throughput but by centralized memory traffic, and that an architecture distributing memory into cores and triggering execution on data readiness can dissolve that bottleneck. They propose MCHA, a multi-tiered hierarchy of memory-centric cores connected by a network-on-chip, and validate it with a cycle-accurate simulator extracted from RTL. If correct, this matters because these workloads are becoming more common, and the paper's measurements indicate GPUs spend 83% to 96% of their operations on data movement rather than useful computation. The authors report that a four-chip MCHA system runs MARL benchmarks between 153 and 2456 times faster than an A100 GPU, reducing DRAM traffic from 96% to as little as 5.44% of operational cycles, while a 32-chip configuration beats specialized accelerators on neuromorphic and graph workloads. The reader should care because the paper proposes a concrete architectural alternative that turns the memory wall into local, peer-to-peer data flow.

What carries the argument

The load-bearing mechanism is the pairing of a multi-tiered peer-to-peer interconnect with an event-driven trigger system. Each MCC bundles a 1KB SRAM data store, instruction memory, a RISC-V core, and hardware FIFOs; a store to an output FIFO address sends a packet to a neighbor, and a load from an input FIFO receives one, with an empty FIFO returning zero to enable a default memory scan. The four trigger types, memory conditional, phase conditional, input, and default memory scan, are all implemented as branch and jump logic in the RISC-V ISA, so data availability controls the program counter and transmission latency hides inside the pipeline. The paper's derivation of a memory-aware speedup formula, where the sequential fraction equals data-transfer time divided by transfer-plus-compute time, is what identifies the global-memory transfer term as the target and motivates the entire distributed-fabric design.

What would settle it

Take the open-source RTL, map a four-chip MCHA onto an FPGA or fabricate a test chip, run the MPE Simple Spread benchmark with 1,000 agents for 1,000 timesteps, and compare measured wall-clock time, DRAM byte counts, and per-core throughput against the simulator's outputs; if real throughput falls well below 1.6 GFLOPS per core or DRAM traffic exceeds 5.44% of memory operations, the central claim collapses.

Watch

Extended reading notes

Core claim

MCHA replaces the centralized global buffer of compute-centric architectures with a distributed memory fabric made of small Memory-Centric Cores (MCCs), each holding local SRAM for entity state and instructions, a RISC-V orchestrator, and MMIO FIFOs that map inter-core communication to ordinary load and store instructions. These cores group into Processing Blocks with high-bandwidth intra-block FIFOs, and blocks connect through a 2D-mesh NoC that extends across chips, forming a three-tier communication pyramid that filters traffic by spatial access frequency. Execution is governed by a data-driven programming model with four triggers: memory conditional, phase conditional, input, and default memory scan, so that a core proceeds when data arrives or local state satisfies a predicate rather than when an instruction stream says so. The paper argues, through a memory-aware reformulation of Gustafson's law, that the sequential fraction of parallel-sequential workloads is dominated by data-transfer time, and MCHA's contribution is to shrink that term by parallelizing and hiding data movement. On its RTL-extracted cycle-accurate simulator, a four-chip MCHA achieves 153.06x to 2456.96x speedup over an NVIDIA A100 on MARL benchmarks, a 32-chip configuration achieves 1.175x over ActiveN on a motor-variable-control neuromorphic workload and up to 3.90x over specialized DSAs on BSP graph processing, and the architecture reduces DRAM access from 96% to 2.26% to 5.44% of operational cycles.

Load-bearing premise

The simulated per-core performance of 1.6 GFLOPS at 200 MHz with only 1KB of SRAM per core is assumed to match real silicon; if the cycle-accurate simulator is optimistic about throughput or if actual workloads spill beyond the tiny local memories into DRAM, the reported 153x to 2456x speedups would shrink.

Editorial extensions

If this is right

  • If the simulator numbers are representative, parallel-sequential workloads can run orders of magnitude faster on a small, low-power MCHA system than on a large GPU, while consuming about 115 milliwatts per chip.
  • Reducing main-memory access from 96% to 5.44% of operations moves MARL workloads from the memory-bound to the compute-bound region of the roofline, so further speedup depends on adding compute throughput rather than bandwidth.
  • Near-linear scaling from four to thirty-two chips for spatially local workloads such as motor-variable control and StarCraft MARL implies the hierarchical fabric avoids creating a new global serialization point.
  • Because inter-chip and global DRAM bandwidth dominate the design-space sensitivity, keeping long-distance traffic sparse through locality-aware entity clustering and dynamic border migration is essential for larger systems.
  • The presented LLM-assisted conversion of a neural network to MCHA programs indicates a pathway toward automating porting, though the paper states that manual porting effort is currently required.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The headline speedup figures include GPU software-stack overhead, notably XLA just-in-time compilation, which the paper reports consumes 97.5% to 99.79% of GPU execution time on these MARL benchmarks; a comparison against hand-optimized CUDA kernels would likely deliver a smaller but still positive speedup.
  • A testable extension is to map the same benchmarks onto an FPGA prototype of MCHA and measure actual DRAM traffic; if real execution shows more than 5.44% DRAM access on MPE Simple Spread, the simulator's memory-traffic claim would need to be revised.
  • The design's advantage is strongest when per-agent state is small and neighborhoods are spatially local; workloads with large state vectors or long-range dependencies could overflow the 1KB per-core SRAM and re-introduce DRAM traffic, narrowing the gap over GPUs.
  • The trigger-based programming model could generalize to other dynamic irregular workloads such as sparse graph neural networks and temporal graph processing, where neighbor sets evolve during execution, since the same input triggers and default scans would handle changing data dependencies.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 4 minor

Summary. The paper proposes MCHA, a memory-centric hierarchical architecture for parallel-sequential workloads (MARL, neuromorphic MVC, and BSP/graph processing). It combines RISC-V based Memory-Centric Cores (MCCs) with a multi-tier NoC (intra-PB, inter-PB mesh, inter-chip links), a data-driven trigger programming model, and a cycle-accurate simulator extracted from RTL. The authors report that a 4-chip system achieves 153.06x–2456.96x speedup over an NVIDIA A100 on MARL workloads while reducing DRAM traffic to 2.26%–5.44% of operations, and they provide 28nm synthesis area/power numbers. Section 7.3.1 later discloses that 97.5%–99.79% of A100 time is XLA JIT compilation overhead, with the normalized architectural speedup being 4.01x–21.93x for MCHA-32. The paper also includes ablation studies, a roofline analysis, and design-space exploration.

Significance. If the quantitative claims hold, MCHA would be a useful data point for memory-centric and data-driven accelerator design: the distributed multi-tier communication fabric and trigger-based programming model are a coherent response to the global-buffer bottleneck in PSC workloads. The paper ships an open-source, RTL-extracted simulator, reports 28nm synthesis area/power, and provides ablation studies, which are concrete strengths. However, the headline speedup is inflated by GPU-side software overhead, and the remaining speedups rest on an unverified per-MCC throughput assumption and on interconnect bandwidth parameters not present in the RTL prototype. These issues are load-bearing for the central claim, so the significance is currently conditional on additional validation.

major comments (4)
  1. [Abstract; Section 7.3.1; Figure 9(b)] The abstract and conclusion present 153.06x–2456.96x as the headline MARL speedup, but Section 7.3.1 shows that 97.5%–99.79% of the A100 execution time is XLA JIT compilation overhead and that the architectural speedup after removing it is only 4.01x–21.93x for MCHA-32. Please make the normalized range the primary claim in the abstract and conclusion, or qualify the large figures explicitly as end-to-end numbers including the baseline's software overhead.
  2. [Table 1; Section 7.3.4] The simulator assumes a processing throughput of 1.6 GFLOPS per MCC at 200 MHz, which implies 8 FLOP/cycle sustained on an RV32I core with 1 KB local SRAM and 8-entry FIFOs. The paper does not document whether this figure comes from RTL synthesis, from simulator measurement, or from an assumed IPC, and no measured silicon performance is reported. Since every speedup scales with this assumption, please state its origin and add a sensitivity analysis connecting MCC throughput to the end-to-end MARL speedups (extending Figure 12(a)–(b) to the workload-level results).
  3. [Section 7.1; Table 1; Figures 8 and 11] The RTL prototype uses SPI chip-to-chip connectors, but the simulator replaces them with PCIe 4.0 parameters and Table 1 assumes 64 GB/s external and 1024 GB/s intra-PB bandwidths. The multi-chip results, especially the MCHA-32 speedups and the scaling curves in Figure 11, therefore rely on interconnect bandwidth that the taped-out design does not provide. Please either model the SPI connectors actually implemented or provide a concrete mapping from the RTL connectors to the assumed commercial link budgets, and quantify how the inter-chip results change at realistic SPI bandwidths.
  4. [Section 7.1; Section 7.2] The simulator is described as cycle-accurate and directly extracted from RTL, but no validation data are reported: there is no comparison between simulator cycle counts and RTL simulation, no FPGA or ASIC measurements, and no error bounds. Given the strong quantitative claims derived entirely from the simulator, please add a validation section showing simulator-versus-RTL agreement for a representative subset of benchmarks and configurations.
minor comments (4)
  1. [Title] The title line contains a typo: 'M emory-Centric' should be 'Memory-Centric'.
  2. [Figure 8 caption] The legend lists 'G3: RTX 2090 Super' in the caption; this GPU model does not exist and should be corrected to the intended NVIDIA part (likely RTX 2080 Super or similar).
  3. [Table 3] The column header 'Core Memory Ops (MB)' mixes units with operation counts; the table would be clearer if the quantity were defined as memory operation volume in MB or as a count, not both.
  4. [Reference [70]] The Dalorex reference has an inconsistent author formatting, with the first author's given name and surname separated oddly from the co-authors; please format it consistently with the other references.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the simulator-based speedups are not derived from the target result, the one same-group baseline (PEARL) is not load-bearing, and the XLA-overhead disclosure is a benchmarking caveat rather than a circular step.

full rationale

After walking the derivation chain, I find no step that reduces to its own inputs by construction. The headline MARL speedups are produced by a separately constructed cycle-accurate simulator that the paper states is 'directly extracted from RTL Verilog HDL implementation' (Section 7.1), not by an analytical formula that assumes the result. Equation (3) is used as motivation for the memory-aware speedup intuition and is not used to generate the reported speedups. The 1.6 GFLOPS/core processing throughput in Table 1 is an input assumption to the simulator, supported by claimed logic synthesis at 200 MHz; it is not a fitted parameter retroactively derived from the target speedups. The comparison includes one same-group baseline, PEARL [67], but that is a published DATE 2025 design used as a normal benchmark, and the central claims against the A100 and other DSAs do not depend on PEARL being weak. The paper itself discloses that after removing GPU-side XLA JIT compilation overhead the architectural speedup is 4.01-21.93x (Section 7.3.1); this shows the abstract's larger 153.06-2456.96x figure is dominated by baseline software overhead. That is a benchmarking or presentation issue, not a circular derivation. Similarly, the simulator's use of commercial PCIe parameters while the RTL prototype uses SPI connectors is a fidelity caveat, not circularity. No equation is self-definitional, no fitted parameter is renamed as a prediction, and no uniqueness argument is imported from the authors' prior work. The appropriate finding is therefore no significant circularity.

Assumptions & free parameters 3 free parameters · 3 assumptions · 0 invented entities

The central claims rest primarily on design parameters chosen by hand for the 28nm implementation and on the assumption that the cycle-accurate simulator captures the RTL faithfully. No new physical entities are introduced. The most consequential free parameter is the 1.6 GFLOPS/core throughput, since the paper does not explain how a standard RV32I RISC-V core achieves it.

free parameters (3)
  • MCC processing throughput = 1.6 GFLOPS/core at 200MHz
    Table 1 assumes each MCC sustains 1.6 GFLOPS while running trigger-based RISC-V code with only 8-entry FIFOs; no silicon measurement confirms this under data-dependent branches.
  • MCC local SRAM capacity = 1KB per MCC
    Table 1; the claim that entity state stays resident and DRAM traffic drops to 5% depends on this capacity being sufficient for the benchmark policies and states.
  • NoC and DRAM bandwidth parameters = 1024 GB/s intra-PB, 64 GB/s external, 409.6 GB/s DRAM
    Table 1; these chosen bandwidths set the multi-tier roofline and the speedup results depend on them.
assumptions (3)
  • domain assumption PSC workloads can be expressed by the three-stage update equation Eq. 1
    The architecture and benchmarks are selected to fit this decomposition; workloads that do not (e.g., highly dynamic graphs) are excluded and listed as a limitation in Section 8.
  • domain assumption The cycle-accurate simulator accurately represents the RTL and physical implementation
    Used throughout Section 7; no measured silicon results are provided to validate the simulator's throughput and bandwidth assumptions.
  • standard math Gustafson speedup formula applies with serial fraction governed by global memory bandwidth
    Used in Eq. 2-3 to motivate the bottleneck; this is a simplified model, not the source of the headline numbers.

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Cite this review

Pith. "Pith review of MCHA: A Memory-Centric Hierarchical Architecture for Parallel-Sequential Computing." pith.science (2026). https://pith.science/paper/6MSO2VJM

@misc{pith2026260804443,
  author       = {Pith},
  title        = {Pith review of: MCHA: A Memory-Centric Hierarchical Architecture for Parallel-Sequential Computing},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/6MSO2VJM}},
  note         = {Machine review of arXiv:2608.04443}
}
abstract

Emerging workloads, such as Multi-Agent Reinforcement Learning (MARL), large-scale neuromorphic computing, and probabilistic graphical models, intrinsically exhibit parallel-sequential computing patterns. While these tasks demand massive parallelism to achieve high throughput, they are severely bottlenecked by irregular data access patterns centralized to main memory. Consequently, conventional architectures face fundamental limitations when executing these workloads, primarily manifesting as global buffer saturation and memory-bound bottlenecks. To address these challenges, we propose the Memory-Centric Hierarchical Architecture (MCHA), a reconfigurable hardware solution tailored for parallel-sequential execution. MCHA leverages a hierarchical communication strategy that facilitates distributed, inter-core data routing, thereby significantly reducing the bandwidth burden on the global memory. Complementing the hardware, MCHA introduces a novel parallel-sequential programming model that utilizes event-driven conditional triggers to effectively hide data transmission latency within the execution pipeline. We benchmark MCHA against a diverse suite of parallel-sequential tasks, including MARL, motor variable control, and Markov random fields. Validated through our open-source, cycle-accurate simulator, MCHA demonstrates performance speedups ranging from 153.06$\times$ to 2456.96$\times$ over NVIDIA A100 GPUs on MARL workloads, while maintaining robust programming flexibility across other application domains. Furthermore, the architecture successfully reduces main memory access from 96% to 5.44%. When synthesized in a 28 nm process, the MCHA implementation occupies an area footprint of 2.92mm$^2$ and consumes 115.36 mW of power at 200 MHz. MCHA is open-sourced at https://github.com/carabdis/MCHA.

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Reference graph

Works this paper leans on

84 extracted references · 72 canonical work pages

  1. [1]

    Norman P Jouppi, Cliff Young, Nishant Patil, David Patterson, Gaurav Agrawal, Raminder Bajwa, Sarah Bates, Suresh Bhatia, Nan Boden, Al Borchers, Rick Boyle, Pierre-luc Cantin, Clifford Chao, Chris Clark, Jeremy Coriell, Mike Daley, Matt Dau, Jeffrey Dean, Ben Gelb, Tara Vazir, Ghaemmaghami, Rajendra Got- tipati, William Gulland, Robert Hagmann, C. Richar...

    2017

  2. [2]

    Loihi: A neuromorphic manycore pro- cessor with on-chip learning

    Mike Davies, Narayan Srinivasa, Tsung-Han Lin, Gau- tham Chinya, Yongqiang Cao, Sri Harsha Choday, Georgios Dimou, Prasad Joshi, Nabil Imam, Shweta Jain, Yuyun Liao, Chit-Kwan Lin, Andrew Lines, Ruokun Liu, Deepak Mathaikutty, Steven McCoy, Arnab Paul, Jonathan Tse, Guruguhanathan Venkatara- manan, Yi-Hsin Weng, Andreas Wild, Yoonseok Yang, and Hong Wang....

    2018

  3. [3]

    Gene M. Amdahl. Validity of the single processor ap- proach to achieving large scale computing capabili- ties. In Spring Joint Computer Conference (SJCC), AFIPS ’67 (Spring), page 483–485, New York, NY , USA,

  4. [4]

    A review of research on SLAM technology based on the fusion of LiDAR and vision

    Peng Chen, Xinyu Zhao, Lina Zeng, Luxinyu Liu, Shengjie Liu, Li Sun, Zaijin Li, Hao Chen, Guojun Liu, Zhongliang Qiao, Yi Qu, Dongxin Xu, Lianhe Li, and Lin Li. A review of research on SLAM technology based on the fusion of LiDAR and vision. Sensors, 25(5):1447, 2025

    2025

  5. [5]

    HgPCN: A hetero- geneous architecture for E2E embedded point cloud inference

    Yiming Gao, Chao Jiang, Wesley Piard, Xiangru Chen, Bhavesh Patel, and Herman Lam. HgPCN: A hetero- geneous architecture for E2E embedded point cloud inference. In ACM/IEEE International Symposium on Microarchitecture (MICRO), pages 1588–1600, 2024. doi: 10.1109/MICRO61859.2024.00116

    arXiv 2024

  6. [6]

    Exploration in deep reinforcement learning: From single-agent to multiagent domain

    Jianye Hao, Tianpei Yang, Hongyao Tang, Chenjia Bai, Jinyi Liu, Zhaopeng Meng, Peng Liu, and Zhen Wang. Exploration in deep reinforcement learning: From single-agent to multiagent domain. IEEE Trans- actions on Neural Networks and Learning Systems, 35 (7):8762–8782, 2023. 15

    work page 2023

  7. [7]

    Deep reinforcement learning for multiagent sys- tems: A review of challenges, solutions, and applica- tions

    Thanh Thi Nguyen, Ngoc Duy Nguyen, and Saeid Naha- vandi. Deep reinforcement learning for multiagent sys- tems: A review of challenges, solutions, and applica- tions. IEEE Transactions on Cybernetics, 50(9):3826– 3839, 2020

    work page 2020

  8. [8]

    A survey on multi-agent reinforcement learning and its application

    Zepeng Ning and Lihua Xie. A survey on multi-agent reinforcement learning and its application. Journal of Automation and Intelligence, 3(2):73–91, 2024

    work page 2024

Show all 84 references
  1. [9]

    Single cortical neurons as deep artificial neural net- works

    David Beniaguev, Idan Segev, and Michael London. Single cortical neurons as deep artificial neural net- works. Neuron, 109(17):2727–2739, 2021

    2021

  2. [10]

    Neuromorphic electronic systems

    Carver Mead. Neuromorphic electronic systems. Pro- ceedings of the IEEE, 78(10):1629–1636, 2002

    2002

  3. [11]

    Towards spike-based machine intelligence with neuromorphic computing

    Kaushik Roy, Akhilesh Jaiswal, and Priyadarshini Panda. Towards spike-based machine intelligence with neuromorphic computing. Nature, 575(7784): 607–617, 2019

    2019

  4. [12]

    A system hierarchy for brain-inspired computing

    Youhui Zhang, Peng Qu, Yu Ji, Weihao Zhang, Guan- grong Gao, Guanrui Wang, Sen Song, Guoqi Li, Wen- guang Chen, Weimin Zheng, Feng Chen, Jing Pei, Rong Zhao, Mingguo Zhao, and Luping Shi. A system hierarchy for brain-inspired computing. Nature, 586 (7829):378–384, 2020

    2020

  5. [13]

    On neural net- works as infinite tree-structured probabilistic graphical models

    Boyao Li, Alexander J Thomson, Houssam Nassif, Matthew M Engelhard, and David Page. On neural net- works as infinite tree-structured probabilistic graphical models. In Conference on Neural Information Process- ing Systems (NeurIPS), volume 37, pages 4598–4628, 2024

    2024

  6. [14]

    Expected probabilistic hi- erarchies

    Marcel Kollovieh, Bertrand Charpentier, Daniel Zügner, and Stephan Günnemann. Expected probabilistic hi- erarchies. In Conference on Neural Information Pro- cessing Systems (NeurIPS), volume 37, pages 13818– 13850, 2024

    2024

  7. [15]

    SINE: Scalable MPE inference for probabilis- tic graphical models using advanced neural embed- dings

    Shivvrat Arya, Tahrima Rahman, and Vibhav Giridhar Gogate. SINE: Scalable MPE inference for probabilis- tic graphical models using advanced neural embed- dings. In International Conference on Artificial Intelli- gence and Statistics (AISTATS), 2025

    2025

  8. [16]

    MapReduce: sim- plified data processing on large clusters

    Jeffrey Dean and Sanjay Ghemawat. MapReduce: sim- plified data processing on large clusters. Communica- tions of the ACM, 51(1):107–113, 2008. ISSN 0001-

    2008

  9. [17]

    Austern, Aart J.C Bik, James C

    Grzegorz Malewicz, Matthew H. Austern, Aart J.C Bik, James C. Dehnert, Ilan Horn, Naty Leiser, and Grze- gorz Czajkowski. Pregel: a system for large-scale graph processing. In ACM SIGMOD International Con- ference on Management of Data (SIGMOD), SIGMOD ’10, page 135–146, New Y...

    2010

  10. [18]

    Franklin, Scott Shenker, and Ion Stoica

    Matei Zaharia, Mosharaf Chowdhury, Tathagata Das, Ankur Dave, Justin Ma, Murphy McCauly, Michael J. Franklin, Scott Shenker, and Ion Stoica. Re- silient distributed datasets: A Fault-Tolerant abstrac- tion for In-Memory cluster computing. In USENIX Symposium on Networked Syste...

  11. [19]

    Poly- graph: Exposing the value of flexibility for graph pro- cessing accelerators

    Vidushi Dadu, Sihao Liu, and Tony Nowatzki. Poly- graph: Exposing the value of flexibility for graph pro- cessing accelerators. In ACM/IEEE Annual Interna- tional Symposium on Computer Architecture (ISCA), pages 595–608. IEEE, 2021

    2021

  12. [20]

    Krste Asanovic, Ras Bodik, Bryan Christopher Catan- zaro, Joseph James Gebis, Parry Husbands, Kurt Keutzer, David A Patterson, William Lester Plishker, John Shalf, Samuel Webb Williams, and Katherine A. Yelick. The landscape of parallel computing research: A view from Berkeley...

    2006

  13. [21]

    Scaling the bandwidth wall: challenges in and avenues for CMP scaling

    Brian M Rogers, Anil Krishna, Gordon B Bell, Ken Vu, Xiaowei Jiang, and Yan Solihin. Scaling the bandwidth wall: challenges in and avenues for CMP scaling. In ACM/IEEE Annual International Symposium on Com- puter Architecture (ISCA), pages 371–382, 2009

    2009

  14. [22]

    Data movement is all you need: A case study on optimizing transformers

    Andrei Ivanov, Nikoli Dryden, Tal Ben-Nun, Shigang Li, and Torsten Hoefler. Data movement is all you need: A case study on optimizing transformers. Proceedings of Machine Learning and Systems, 3:711–732, 2021

    2021

  15. [23]

    A quantitative study of irregular programs on GPUs

    Martin Burtscher, Rupesh Nasre, and Keshav Pingali. A quantitative study of irregular programs on GPUs. In IEEE International Symposium on Workload Character- ization (IISWC), pages 141–151. IEEE, 2012

    2012

  16. [24]

    Scheduling page table walks for irregular gpu applications

    Seunghee Shin, Guilherme Cox, Mark Oskin, Gabriel H Loh, Yan Solihin, Abhishek Bhattacharjee, and Arkaprava Basu. Scheduling page table walks for irregular gpu applications. In ACM/IEEE Annual International Symposium on Computer Architecture (ISCA), pages 180–192. IEEE Compute...

    2018

  17. [25]

    Plasticine: A reconfigurable architecture for parallel paterns

    Raghu Prabhakar, Yaqi Zhang, David Koeplinger, Matt Feldman, Tian Zhao, Stefan Hadjis, Ardavan Pedram, Christos Kozyrakis, and Kunle Olukotun. Plasticine: A reconfigurable architecture for parallel paterns. In ACM/IEEE Annual International Symposium on Com- puter Architecture ...

    2017

  18. [26]

    Shah, Zhengyu Chen, Kaizhao Liang, Swayambhoo Jain, Urmish Thakker, Dawei Huang, Sumti Jairath, Kevin J

    Raghu Prabhakar, Ram Sivaramakrishnan, Darshan Gandhi, Yun Du, Mingran Wang, Xiangyu Song, Ke- jie Zhang, Tianren Gao, Angela Wang, Xiaoyan Li, Yongning Sheng, Joshua Brot, Denis Sokolov, Apurv Vivek, Calvin Leung, Arjun Sabnis, Jiayu Bai, Tuowen Zhao, Mark Gottscho, David Jac...

    2024

  19. [27]

    Leviathan: A unified system for general-purpose near-data com- puting

    Brian C Schwedock and Nathan Beckmann. Leviathan: A unified system for general-purpose near-data com- puting. In ACM/IEEE International Symposium on Microarchitecture (MICRO), pages 1278–1294. IEEE, 2024

    2024

  20. [28]

    CGRA-ME: A unified framework for CGRA mod- elling and exploration

    S Alexander Chin, Noriaki Sakamoto, Allan Rui, Jim Zhao, Jin Hee Kim, Yuko Hara-Azumi, and Jason An- derson. CGRA-ME: A unified framework for CGRA mod- elling and exploration. In IEEE International Confer- ence on Application-Specific Systems, Architectures and Processors (ASA...

    2017

  21. [29]

    Enhancing cgra efficiency through aligned compute and communica- tion provisioning

    Zhaoying Li, Pranav Dangi, Chenyang Yin, Thilini Kaushalya Bandara, Rohan Juneja, Cheng Tan, Zhenyu Bai, and Tulika Mitra. Enhancing cgra efficiency through aligned compute and communica- tion provisioning. In ACM International Conference on Architectural Support for Programmi...

    2025

  22. [30]

    PICACHU: Plug-in CGRA handling up- coming nonlinear operations in LLMs

    Jiajun Qin, Tianhua Xia, Cheng Tan, Jeff Zhang, and Sai Qian Zhang. PICACHU: Plug-in CGRA handling up- coming nonlinear operations in LLMs. In ACM Inter- national Conference on Architectural Support for Pro- gramming Languages and Operating Systems, pages 845–861, 2025

    2025

  23. [31]

    Compute caches

    Shaizeen Aga, Supreet Jeloka, Arun Subramaniyan, Satish Narayanasamy, David Blaauw, and Reetuparna Das. Compute caches. In IEEE International Sym- posium on High Performance Computer Architecture (HPCA), pages 481–492. IEEE, 2017

    2017

  24. [32]

    The MIT Alewife machine: Architecture and perfor- mance

    Anant Agarwal, Ricardo Bianchini, David Chaiken, Kirk L Johnson, David Kranz, John Kubiatowicz, Beng- Hong Lim, Kenneth Mackenzie, and Donald Yeung. The MIT Alewife machine: Architecture and perfor- mance. ACM SIGARCH Computer Architecture News, 23(2):2–13, 1995

    1995

  25. [33]

    Graph prefetch- ing using data structure knowledge

    Sam Ainsworth and Timothy M Jones. Graph prefetch- ing using data structure knowledge. In International Conference on Supercomputing (ICS), pages 1–11, 2016

    2016

  26. [34]

    An event- triggered programmable prefetcher for irregular work- loads

    Sam Ainsworth and Timothy M Jones. An event- triggered programmable prefetcher for irregular work- loads. ACM Sigplan Notices, 53(2):578–592, 2018

    2018

  27. [35]

    HEAT: NPU-NDP heterogeneous archi- tecture for transformer-empowered graph neural net- works

    Ruiyang Chen, Zhuoran Song, Yicheng Zheng, Zeyu Zhu, Gang Li, Naifeng Jing, Xiaoyao Liang, and Haib- ing Guan. HEAT: NPU-NDP heterogeneous archi- tecture for transformer-empowered graph neural net- works. In ACM/IEEE International Symposium on Mi- croarchitecture (MICRO), page...

    2025

  28. [38]

    Pimba: A processing-in-memory acceleration for post-transformer large language model serving

    Wonung Kim, Yubin Lee, Yoonsung Kim, Jinwoo Hwang, Seongryong Oh, Jiyong Jung, Aziz Huseynov, Woong Park, Chang Park, Divya Mahajan, and Jongse Park. Pimba: A processing-in-memory acceleration for post-transformer large language model serving. In ACM/IEEE International Symposi...

    2025 doi

  29. [39]

    StreamPIM: Streaming matrix computation in racetrack memory

    Yuda An, Yunxiao Tang, Shushu Yi, Li Peng, Xiurui Pan, Guangyu Sun, Zhaochu Luo, Qiao Li, and Jie Zhang. StreamPIM: Streaming matrix computation in racetrack memory. In IEEE International Symposium on High-Performance Computer Architecture (HPCA), pages 297–311, 2024. doi: 10....

    2024

  30. [40]

    MoCA: Memory-centric, adaptive execution for multi-tenant deep neural networks

    Seah Kim, Hasan Genc, Vadim Vadimovich Nikiforov, Krste Asanović, Borivoje Nikolić, and Yakun Sophia Shao. MoCA: Memory-centric, adaptive execution for multi-tenant deep neural networks. In IEEE Interna- tional Symposium on High-Performance Computer Ar- chitecture (HPCA), page...

    2023

  31. [42]

    Abellán, Ajay Joshi, David Kaeli, and John Kim

    Hyojun Son, Gilbert Jonatan, Xiangyu Wu, Haeyoon Cho, Kaustubh Shivdikar, José L. Abellán, Ajay Joshi, David Kaeli, and John Kim. PIMnet: A domain-specific network for efficient collective communication in scal- able PIM. In IEEE International Symposium on High- Performance Co...

    2025

  32. [44]

    Be- yond page migration: Enhancing tiered memory per- formance via integrated last-level cache management and page migration

    Hwanjun Lee, Minho Kim, Yeji Jung, Seonmu Oh, Ki- Dong Kang, Seunghak Lee, and Daehoon Kim. Be- yond page migration: Enhancing tiered memory per- formance via integrated last-level cache management and page migration. In ACM/IEEE International Sym- posium on Microarchitecture ...

    2025

  33. [45]

    Re- architecting end-host networking with CXL: Coher- ence, memory, and offloading

    Houxiang Ji, Yifan Yuan, Yang Zhou, Ipoom Jeong, Ren Wang, Saksham Agarwal, and Nam Kim. Re- architecting end-host networking with CXL: Coher- ence, memory, and offloading. In ACM/IEEE Inter- national Symposium on Microarchitecture (MICRO), pages 1809–1823, 10 2025. doi: 10.11...

    2025 doi

  34. [46]

    Systematic CXL memory characterization and performance analysis at scale

    Jinshu Liu, Hamid Hadian, Yuyue Wang, Daniel Berger, Marie Nguyen, Xun Jian, Sam Noh, and Huaicheng Li. Systematic CXL memory characterization and performance analysis at scale. In ACM Interna- tional Conference on Architectural Support for Pro- gramming Languages and Operatin...

    2025

  35. [47]

    M5: Mastering page migration and memory management for CXL-based tiered memory systems

    Yan Sun, Jongyul Kim, Zeduo Yu, Jiyuan Zhang, Siyuan Chai, Michael Kim, Hwayong Nam, Jaehyun Park, Eo- jin Na, Yifan Yuan, Ren Wang, Jung Ho Ahn, Tianyin Xu, and Nam Kim. M5: Mastering page migration and memory management for CXL-based tiered memory systems. In ACM Internation...

    2025

  36. [48]

    Williams, Yashas Lokesh, and Praveen Ravi

    J Terry, Benjamin Black, Nathaniel Grammel, Mario Jayakumar, Ananth Hari, Ryan Sullivan, Luis S Santos, Clemens Dieffendahl, Caroline Horsch, Rodrigo Perez- Vicente, Caroline Horsch, Clemens Dieffendahl, Niall L. Williams, Yashas Lokesh, and Praveen Ravi. Petting- zoo: Gym for...

    2021

  37. [49]

    JaxMARL: Multi-agent rl environments and algorithms in JAX

    Alexander Rutherford, Benjamin Ellis, Matteo Gal- lici, Jonathan Cook, Andrei Lupu, Garðar Ingvars- son, Timon Willi, Ravi Hammond, Akbir Khan, Chris- tian Schroeder de Witt, Alexandra Souly, Saptarashmi Bandyopadhyay, Mikayel Samvelyan, Minqi Jiang, Robert Tjarko Lange, Shimo...

    2024

  38. [50]

    Learning to communicate with deep multi-agent reinforcement learning

    Jakob Foerster, Yannis M Assael, Nando de Freitas, and Shimon Whiteson. Learning to communicate with deep multi-agent reinforcement learning. In Con- ference on Neural Information Processing Systems (NeurIPS), pages 2137–2145, 2016

    2016

  39. [51]

    Model-free opponent shaping

    Christopher Lu, Timon Willi, Christian A Schroeder De Witt, and Jakob Foerster. Model-free opponent shaping. In International Conference on Machine Learning (ICML), pages 14398–14411. PMLR, 2022

    2022

  40. [52]

    Learning with opponent-learning awareness

    Jakob Foerster, Richard Chen, Maruan Al-Shedivat, Shimon Whiteson, Pieter Abbeel, and Igor Mordatch. Learning with opponent-learning awareness. In Inter- national Conference on Autonomous Agents and Mul- tiAgent Systems (AAMAS), pages 122–130, 07 2018. doi: 10.65109/HGWA8807

    2018 doi

  41. [53]

    Reevaluating Amdahl’s law

    John L Gustafson. Reevaluating Amdahl’s law. Com- munications of the ACM, 31(5):532–533, 1988

    1988

  42. [54]

    NVIDIA tesla: A unified graphics and computing architecture

    Erik Lindholm, John Nickolls, Stuart Oberman, and John Montrym. NVIDIA tesla: A unified graphics and computing architecture. IEEE Micro, 28(2):39–55, 2008

    2008

  43. [55]

    Some computer organizations and their effectiveness

    Michael J Flynn. Some computer organizations and their effectiveness. IEEE Transactions on Computers, 100(9):948–960, 2009

    2009

  44. [56]

    Cerebras architecture deep dive: First look inside the hardware/software co-design for deep learn- ing

    Lie, Sean. Cerebras architecture deep dive: First look inside the hardware/software co-design for deep learn- ing. IEEE Micro, 43(3):18–30, 2023

    2023

  45. [57]

    PCI express and advanced switching: Evolutionary path to building next generation interconnects

    David Mayhew and Venkata Krishnan. PCI express and advanced switching: Evolutionary path to building next generation interconnects. In IEEE Symposium on High Performance Interconnects (HOTI), pages 21–29. IEEE, 2003

    2003

  46. [58]

    Universal chiplet interconnect ex- press (UCIe): An open industry standard for innova- tions with chiplets at package level

    Debendra Das Sharma, Gerald Pasdast, Zhiguo Qian, and Kemal Aygun. Universal chiplet interconnect ex- press (UCIe): An open industry standard for innova- tions with chiplets at package level. IEEE Transactions on Components, Packaging and Manufacturing Tech- nology, 12(9):1423...

    2022

  47. [59]

    NVIDIA Hopper H100 GPU: Scaling performance

    Choquette, Jack. NVIDIA Hopper H100 GPU: Scaling performance. IEEE Micro, 43(3):9–17, 2023

    2023

  48. [60]

    Princi- ples and practices of interconnection networks

    William James Dally and Brian Patrick Towles. Princi- ples and practices of interconnection networks. Else- vier, 2004

    2004

  49. [61]

    K-means cluster- ing algorithms: A comprehensive review, variants anal- ysis, and advances in the era of big data

    Abiodun M Ikotun, Absalom E Ezugwu, Laith Abuali- gah, Belal Abuhaija, and Jia Heming. K-means cluster- ing algorithms: A comprehensive review, variants anal- ysis, and advances in the era of big data. Information Sciences, 622:178–210, 2023

    2023

  50. [62]

    More recent advances in (Hyper)Graph partitioning

    Ümit Çatalyürek, Karen Devine, Marcelo Faraj, Lars Gottesbüren, Tobias Heuer, Henning Meyerhenke, Peter Sanders, Sebastian Schlag, Christian Schulz, Daniel Seemaier, and Dorothea Wagner. More recent advances in (Hyper)Graph partitioning. ACM Comput- ing Surveys, 55(12):1–38, 2023

    2023

  51. [63]

    Emergence of grounded compositional language in multi-agent pop- ulations

    Igor Mordatch and Pieter Abbeel. Emergence of grounded compositional language in multi-agent pop- ulations. In AAAI Conference on Artificial Intelligence (AAAI), 2017

    2017

  52. [64]

    FACMAC: Factored multi- agent centralised policy gradients

    Bei Peng, Tabish Rashid, Christian Schroeder de Witt, Pierre-Alexandre Kamienny, Philip Torr, Wendelin Böh- mer, and Shimon Whiteson. FACMAC: Factored multi- agent centralised policy gradients. In Conference on Neural Information Processing Systems (NeurIPS), vol- ume 34, page...

    2021

  53. [65]

    ReSA: Reconfig- urable systolic array for multiple tiny dnn tensors

    Ching-Jui Lee and Tsung Tai Yeh. ReSA: Reconfig- urable systolic array for multiple tiny dnn tensors. ACM Transactions on Architecture and Code Optimization, 21(3):1–24, 2024

    2024

  54. [66]

    DeepSeek-R1 incentivizes reasoning in LLMs through reinforcement learning

    DeepSeek-AI. DeepSeek-R1 incentivizes reasoning in LLMs through reinforcement learning. Nature, 645 (8081):633–638, 2025

    2025

  55. [67]

    PEARL: FPGA-based reinforcement learning acceler- ation with pipelined parallel environments

    Jiayi Li, Hongxiao Zhao, Wenshuo Yue, Yihan Fu, Dai- jing Shi, Anjunyi Fan, Yuchao Yang, and Bonan Yan. PEARL: FPGA-based reinforcement learning acceler- ation with pipelined parallel environments. In De- sign, Automation & Test in Europe Conference (DATE), pages 1–7. IEEE, 2025

    2025

  56. [68]

    ActiveN: a scalable and flexibly- programmable event-driven neuromorphic processor

    Xiaoyi Liu, Zhongzhu Pu, Peng Qu, Weimin Zheng, and Youhui Zhang. ActiveN: a scalable and flexibly- programmable event-driven neuromorphic processor. In ACM/IEEE International Symposium on Microarchi- tecture (MICRO), pages 1122–1137. IEEE, 2024

    2024

  57. [69]

    MC 2A: Enabling algorithm-hardware co-design for efficient markov chain monte carlo acceleration

    Shirui Zhao, Jun Yin, Lingyun Yao, Martin Andraud, Wannes Meert, and Marian Verhelst. MC 2A: Enabling algorithm-hardware co-design for efficient markov chain monte carlo acceleration. arXiv preprint arXiv:2507.12935, 2025

    2025 arXiv

  58. [70]

    Dalorex: A data-local program execution and architecture for memory-bound appli- cations

    Marcelo Orenes-Vera, Esin Tureci, David Wentzlaff, Margaret Martonosi. Dalorex: A data-local program execution and architecture for memory-bound appli- cations. In IEEE International Symposium on High- Performance Computer Architecture (HPCA), pages 718–730. IEEE, 2023

    2023

  59. [71]

    A multi-scale layer-resolved spiking net- work model of resting-state dynamics in macaque vi- sual cortical areas

    Maximilian Schmidt, Rembrandt Bakker, Kelly Shen, Gleb Bezgin, Markus Diesmann, and Sacha Jennifer van Albada. A multi-scale layer-resolved spiking net- work model of resting-state dynamics in macaque vi- sual cortical areas. PLOS Computational Biology, 14 (10):e1006359, 2018

    2018

  60. [72]

    The PageRank citation ranking: Bring- ing order to the web

    Lawrence Page, Sergey Brin, Rajeev Motwani, and Terry Winograd. The PageRank citation ranking: Bring- ing order to the web. Technical report, Stanford infolab, 1999

    1999

  61. [73]

    Introducing the graph 500

    Richard C Murphy, Kyle B Wheeler, Brian W Barrett, and James A Ang. Introducing the graph 500. Cray Users Group (CUG), 19(45-74):22, 2010

    2010

  62. [74]

    Statistical ro- bustness of markov chain monte carlo accelerators

    Xiangyu Zhang, Ramin Bashizade, Yicheng Wang, Sayan Mukherjee, and Alvin R Lebeck. Statistical ro- bustness of markov chain monte carlo accelerators. In ACM International Conference on Architectural Sup- port for Programming Languages and Operating Sys- tems (ASPLOS), pages 95...

    2021

  63. [75]

    AIA: A 16nm multicore SoC for approximate inference acceleration exploiting non- normalized knuth-yao sampling and inter-core regis- ter sharing

    Shirui Zhao, Nimish Shah, Wannes Meert, and Mar- ian Verhelst. AIA: A 16nm multicore SoC for approximate inference acceleration exploiting non- normalized knuth-yao sampling and inter-core regis- ter sharing. In IEEE European Solid-State Electronics Research Conference (ESSERC...

    2024

  64. [76]

    A 3mm2 programmable bayesian in- ference accelerator for unsupervised machine percep- tion using parallel gibbs sampling in 16nm

    Glenn G Ko, Yuji Chai, Marco Donato, Paul N What- mough, Thierry Tambe, Rob A Rutenbar, David Brooks, and Gu-Yeon Wei. A 3mm2 programmable bayesian in- ference accelerator for unsupervised machine percep- tion using parallel gibbs sampling in 16nm. In IEEE Symposium on VLSI Ci...

    2020

  65. [77]

    Mea- surement and analysis of online social networks

    Alan Mislove, Massimiliano Marcon, Krishna P Gum- madi, Peter Druschel, and Bobby Bhattacharjee. Mea- surement and analysis of online social networks. In ACM SIGCOMM Conference on Internet Measurement (IMC), pages 29–42, 2007

    2007

  66. [78]

    Kronecker graphs: an approach to modeling networks

    Jure Leskovec, Deepayan Chakrabarti, Jon Kleinberg, Christos Faloutsos, Zoubin Ghahramani. Kronecker graphs: an approach to modeling networks. Journal of Machine Learning Research, 11(2), 2010

    2010

  67. [79]

    NeuroEngine: A hardware-based event- driven simulation system for advanced brain-inspired 19 computing

    Hunjun Lee, Chanmyeong Kim, Yujin Chung, and Jang- woo Kim. NeuroEngine: A hardware-based event- driven simulation system for advanced brain-inspired 19 computing. In ACM International Conference on Archi- tectural Support for Programming Languages and Op- erating Systems (ASP...

    2021

  68. [80]

    XLA : Compiling Machine Learning for Peak Performance, 2020

    Amit Sabne. XLA : Compiling Machine Learning for Peak Performance, 2020

    2020

  69. [81]

    A scalable processing-in- memory accelerator for parallel graph processing

    Junwhan Ahn, Sungpack Hong, Sungjoo Yoo, Onur Mutlu, and Kiyoung Choi. A scalable processing-in- memory accelerator for parallel graph processing. In ACM/IEEE Annual International Symposium on Com- puter Architecture (ISCA), pages 105–117. IEEE, 2015

    2015

  70. [82]

    A full-system perspective on UPMEM performance

    Birte Friesel, Marcel Lütke Dreimann, and Olaf Spinczyk. A full-system perspective on UPMEM performance. In The Workshop on Disruptive Memory Systems (DIMES), pages 1–7, 2023

    2023

  71. [83]

    Minnow: Lightweight offload engines for worklist management and worklist-directed prefetch- ing

    Dan Zhang, Xiaoyu Ma, Michael Thomson, and Derek Chiou. Minnow: Lightweight offload engines for worklist management and worklist-directed prefetch- ing. ACM SIGPLAN Notices, 53(2):593–607, 2018

    2018

  72. [84]

    GraphR: Accelerating graph processing us- ing ReRAM

    Linghao Song, Youwei Zhuo, Xuehai Qian, Hai Li, and Yiran Chen. GraphR: Accelerating graph processing us- ing ReRAM. In IEEE International Symposium on High- Performance Computer Architecture (HPCA), pages 531–543. IEEE, 2018

    2018

  73. [85]

    ExTensor: An accelerator for sparse tensor algebra

    Kartik Hegde, Hadi Asghari-Moghaddam, Michael Pel- lauer, Neal Crago, Aamer Jaleel, Edgar Solomonik, Joel Emer, and Christopher W Fletcher. ExTensor: An accelerator for sparse tensor algebra. In ACM/IEEE In- ternational Symposium on Microarchitecture (MICRO), pages 319–333, 2019

    2019

  74. [782]

    URL https: //doi.org/10.1145/1327452.1327492

    doi: 10.1145/1327452.1327492. URL https: //doi.org/10.1145/1327452.1327492

  75. [1967]

    ISBN 9781450378956

    Association for Computing Machinery. ISBN 9781450378956. doi: 10.1145/1465482.1465560. URL https://doi.org/10.1145/1465482.1465560

  76. [2012]

    ISBN 978-931971-92-8

    USENIX Association. ISBN 978-931971-92-8. URL https://www.usenix.org/conference/nsdi12/ technical-sessions/presentation/zaharia

Pith tools

Reviewed August 11, 2026 · model on record in the stance chip above.