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CODA: Enabling Co-location of Computation and Data for Near-Data Processing

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arxiv 1710.09517 v1 pith:NVJOV7XA submitted 2017-10-26 cs.AR

classification cs.AR
keywords memorymodulesdatanear-dataaccessaddresschallengecomputation
verification ladder T0 review T1 audit T2 compute T3 formal

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Recent studies have demonstrated that near-data processing (NDP) is an effective technique for improving performance and energy efficiency of data-intensive workloads. However, leveraging NDP in realistic systems with multiple memory modules introduces a new challenge. In today's systems, where no computation occurs in memory modules, the physical address space is interleaved at a fine granularity among all memory modules to help improve the utilization of processor-memory interfaces by distributing the memory traffic. However, this is at odds with efficient use of NDP, which requires careful placement of data in memory modules such that near-data computations and their exclusively used data can be localized in individual memory modules, while distributing shared data among memory modules to reduce hotspots. In order to address this new challenge, we propose a set of techniques that (1) enable collections of OS pages to either be fine-grain interleaved among memory modules (as is done today) or to be placed contiguously on individual memory modules (as is desirable for NDP private data), and (2) decide whether to localize or distribute each memory object based on its anticipated access pattern and steer computations to the memory where the data they access is located. Our evaluations across a wide range of workloads show that the proposed mechanism improves performance by 31% and reduces 38% remote data accesses over a baseline system that cannot exploit computate-data affinity characteristics.

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Cited by 1 Pith paper

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  1. NUNA: Characterizing and Mitigating Non-Uniform Network Access in Multi-Die GPU Scale-Up Systems

    cs.DC 2026-08 conditional novelty 7.0 of 10

    In multi-die GPU scale-up systems, placing communication threadblocks and memory near I/O ports and routing traffic to nearby ports speeds up small collectives by up to 1.8x and LLM inference decode by 7% on average.

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