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Architecture and performance of Devito, a system for automated stencil computation

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arxiv 1807.03032 v3 pith:3CBKVU5T submitted 2018-07-09 cs.MS

classification cs.MS
keywords devitoperformancestencilcompilerequationsoptimizationsapplicationsarchitecture
verification ladder T0 review T1 audit T2 compute T3 formal

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Stencil computations are a key part of many high-performance computing applications, such as image processing, convolutional neural networks, and finite-difference solvers for partial differential equations. Devito is a framework capable of generating highly-optimized code given symbolic equations expressed in Python, specialized in, but not limited to, affine (stencil) codes. The lowering process---from mathematical equations down to C++ code---is performed by the Devito compiler through a series of intermediate representations. Several performance optimizations are introduced, including advanced common sub-expressions elimination, tiling and parallelization. Some of these are obtained through well-established stencil optimizers, integrated in the back-end of the Devito compiler. The architecture of the Devito compiler, as well as the performance optimizations that are applied when generating code, are presented. The effectiveness of such performance optimizations is demonstrated using operators drawn from seismic imaging applications.

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Cited by 2 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. An Event-Driven Approach to Serverless Seismic Imaging in the Cloud

    cs.DC 2019-09 conditional novelty 6.0 of 10

    An event-driven serverless workflow on AWS Batch, Lambda, Step Functions and S3 runs large-scale least-squares seismic imaging with less idle cost and automatic resilience to instance failures.

  2. Performance of Devito on HPC-Optimised ARM Processors

    cs.PF 2019-08 conditional novelty 4.0 of 10

    Devito-generated acoustic and TTI seismic kernels run at comparable single-socket speed on ARM ThunderX2 as on Intel Xeon for memory-bound workloads.

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