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MRAM Co-designed Processing-in-Memory CNN Accelerator for Mobile and IoT Applications

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arxiv 1811.12179 v1 pith:2PKPBR3I submitted 2018-11-26 eess.SP

Baohua Sun , Daniel Liu , Leo Yu , Jay Li , Helen Liu , Wenhan Zhang , Terry Torng This is my paper · ORCID
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keywords applicationsmramco-designeddevicemobileacceleratorarchitecturebeen
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We designed a device for Convolution Neural Network applications with non-volatile MRAM memory and computing-in-memory co-designed architecture. It has been successfully fabricated using 22nm technology node CMOS Si process. More than 40MB MRAM density with 9.9TOPS/W are provided. It enables multiple models within one single chip for mobile and IoT device applications.

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Cited by 1 Pith paper

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  1. FLARE: FP-Less PTQ and Low-ENOB ADC Based AMS-PiM for Error-Resilient, Fast, and Efficient Transformer Acceleration

    cs.LG 2024-11 conditional novelty 6.0 of 10

    FLARE replaces floating-point quantization and softmax in transformers with integer-only eMSB-based methods and low-ENOB analog-to-digital converters, aiming for fast and low-energy attention.

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