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arxiv: 1907.01451 · v1 · pith:AUGDQFYCnew · submitted 2019-07-01 · 💻 cs.ET

Evolution of Technologies and Multivalued Circuits

Daniel Etiemble This is my paper

Pith reviewed 2026-05-25 11:35 UTC · model grok-4.3

classification 💻 cs.ET
keywords multi-valued logicMVL circuitsbinary circuitsIC technology scalingnoise marginspower dissipationquantum devices
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The pith

The evolution of IC technologies increases the disadvantages of multi-valued logic circuits versus binary ones.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper reviews decades of multi-valued logic circuit proposals and explains their repeated lack of success through basic limits on noise margins, power, and complexity. It observes that every advance in circuit technology prompts new MVL designs, yet scaling trends in mainstream technologies widen rather than close the performance gap with binary circuits. Only quantum devices are singled out as a possible exception among emerging approaches, though even those face severe implementation barriers and narrow use cases.

Core claim

For more than 45 years, many multi-valued circuits have been presented. With very rare exceptions, they have been unsuccessful for fundamental reasons that can be explained. Each time a new circuit technology is presented, a lot of new MVL circuits are proposed. Can new circuit technologies overcome the fundamental disadvantages of MVL circuits? The evolution of IC technologies in the last decades unfortunately increases the disadvantage of MVL circuits versus binary ones. For non conventional technologies, only quantum devices look promising, even if implementation is challenging and applications are restricted to a small niche.

What carries the argument

The persistent comparison of noise margins, power dissipation, and implementation complexity between multi-valued and binary circuits as device technologies scale.

If this is right

  • Binary IC scaling trends will continue to enlarge the performance gap favoring binary circuits over MVL.
  • Non-quantum emerging technologies will not remove the fundamental barriers that have blocked MVL adoption.
  • Quantum devices remain the sole candidate class that could support MVL, but only within restricted niches.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Research investment in MVL for conventional or near-conventional device platforms is unlikely to yield practical results.
  • If multi-valued operation is required, device physics efforts would need to prioritize quantum-effect structures over classical scaling.
  • Binary circuit dominance may extend indefinitely unless device-level noise and power properties change at the physical level.

Load-bearing premise

The core drawbacks of multi-valued circuits in noise margins, power, and complexity will remain or grow worse under continued binary technology scaling without help from non-quantum alternatives.

What would settle it

A fabricated multi-valued circuit in a scaled mainstream technology that matches or exceeds binary performance on noise margin, power per function, and area.

Figures

Figures reproduced from arXiv: 1907.01451 by Daniel Etiemble.

Figure 1
Figure 1. Figure 1: General scheme of M-valued circuits. Interconnection issues have been quoted for binary circuits: they are probably the most important argument for promoting M-valued circuits. Let’s consider again [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Bipolar circuitries Significant static power dissipation has excluded the pMOS and NMOS versions for which a current flows from power supply to ground when the output transistor is on. It also excludes any binary or M-valued CMOS version that would be based on a differential pair as in ECL circuits. It also excludes current mode circuits that are based on different levels of currents. 2 [PITH_FULL_IMAGE:f… view at source ↗
Figure 3
Figure 3. Figure 3: CMOS technological nodes [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Vdd scaling since 1000-nm node 1) CMOS voltage mode M-valued circuits: As the smallest Vdd value compatible with a correct behavior of transistors must be used to reduce power dissipation, it means that the different values of M-valued circuits must be included in the Vdd range: 0, Vdd/2 and Vdd for ternary circuits or 0, Vdd/3, 2 Vdd/3 and Vdd for quaternary circuits. This is more and more difficult with … view at source ↗
Figure 5
Figure 5. Figure 5: 4-valued inverter proposed in [16] M-valued memories as it has several thresholds in the non￾monotonic, oscillatory ID-VG characteristics. A lot of papers have been presented in the 90s and far less in the last two decades. SET devices had to solve two types of problems: • Being able to operate at normal temperature, as SET devices don’t exhibit such performance advantage to justify to operate a very low t… view at source ↗
Figure 6
Figure 6. Figure 6: (a)Schematic of SET ; (b) Schematic of equivalent circuit [PITH_FULL_IMAGE:figures/full_fig_p005_6.png] view at source ↗
Figure 8
Figure 8. Figure 8: shows that this quantum computer has few similitudes with the computers that we usually use. A previous IBM project with supraconducting technologies in the 80s has shown that it is not easy to make mature a technology close to absolute zero. Quantum devices are probably the only actual M-valued devices. If quantum computing looks very promising, it will probably remain an important, but small niche (coole… view at source ↗
read the original abstract

For more than 45 years, many multi-valued circuits have been presented. With very rare exceptions, they have been unsuccessful for fundamental reasons that can be explained. Each time a new circuit technology is presented, a lot of new MVL circuits are proposed. Can new circuit technologies overcome the fundamental disadvantages of MVL circuits? The evolution of IC technologies in the last decades unfortunately increases the disadvantage of MVL circuits versus binary ones. For non conventional technologies, only quantum devices look promising, even if implementation is challenging and applications are restricted to a small niche.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

1 major / 0 minor

Summary. The manuscript reviews more than 45 years of multi-valued logic (MVL) circuit proposals, attributes their commercial failure to fundamental disadvantages (noise margins, power consumption, and circuit complexity), and argues that continued scaling of conventional IC technologies has increased these disadvantages relative to binary circuits. It concludes that, among non-conventional technologies, only quantum devices remain potentially viable, albeit with severe implementation challenges and restricted niche applications.

Significance. If the historical synthesis is accepted, the paper supplies a cautionary perspective that could help redirect research effort away from repeated MVL attempts in conventional technologies and toward quantum or binary alternatives. Its breadth of historical coverage is a modest strength, but the absence of quantitative models, error analysis, or new supporting data limits its ability to generate falsifiable predictions or alter technical practice.

major comments (1)
  1. [Abstract] Abstract: the central claim that 'the evolution of IC technologies in the last decades unfortunately increases the disadvantage of MVL circuits versus binary ones' is presented as a qualitative historical judgment without accompanying quantitative metrics, scaling-law references, or comparative data on parameters such as supply voltage, noise margins, or interconnect complexity; this interpretive step is load-bearing for the final recommendation yet remains unsupported within the manuscript.

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for the constructive comments. We address the major comment below.

read point-by-point responses

  1. Referee: [Abstract] Abstract: the central claim that 'the evolution of IC technologies in the last decades unfortunately increases the disadvantage of MVL circuits versus binary ones' is presented as a qualitative historical judgment without accompanying quantitative metrics, scaling-law references, or comparative data on parameters such as supply voltage, noise margins, or interconnect complexity; this interpretive step is load-bearing for the final recommendation yet remains unsupported within the manuscript.

    Authors: The manuscript is a historical synthesis of more than 45 years of MVL proposals, attributing their commercial failure to fundamental disadvantages (noise margins, power consumption, circuit complexity) that are explained in the body of the paper. The claim about IC technology evolution follows directly from how documented scaling trends—such as reduced supply voltages—amplify those same disadvantages for multi-level signals relative to binary ones. While the paper does not introduce new quantitative models or simulations, the interpretation rests on the empirical pattern of repeated failures and established circuit theory. We will revise the manuscript to include explicit references to CMOS scaling literature addressing voltage reduction, noise margins, and interconnect effects to make this connection more explicit. revision: yes

Circularity Check

0 steps flagged

No significant circularity identified

full rationale

The paper is an opinion and historical analysis piece without equations, fitted parameters, derivations, or quantitative models. Its claims rest on interpretations of external historical MVL outcomes over 45 years and observed IC scaling trends, with no internal chain that reduces by construction to its own inputs or self-citations. The argument is self-contained against external benchmarks and does not invoke any of the enumerated circularity patterns.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The conclusions rest on the domain assumption that historical MVL failures reflect persistent, technology-independent disadvantages that scaling will exacerbate; no free parameters or invented entities are introduced.

axioms (1)
  • domain assumption Historical failures of MVL circuits indicate fundamental disadvantages that new non-quantum technologies will not overcome.
    This premise underpins the claim that technology evolution increases MVL disadvantages.

pith-pipeline@v0.9.0 · 5601 in / 1080 out tokens · 27646 ms · 2026-05-25T11:35:56.433454+00:00 · methodology

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Reference graph

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