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arxiv: 1907.02968 · v1 · pith:3JXW2G7Enew · submitted 2019-07-05 · ⚛️ physics.ins-det

Data and clock transmission interface for the WCDA in LHAASO

Shaoping Chu , Lei Zhao , Zouyi Jiang , Cong Ma , Xingshun Gao , Yunfan Yang , Shubin Liu , Qi An This is my paper

Pith reviewed 2026-05-25 02:00 UTC · model grok-4.3

classification ⚛️ physics.ins-det
keywords White Rabbitclock synchronizationdata transmissionLHAASO WCDAfront end electronicsphotomultiplier tubestriggerless readout
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The pith

A prototype using White Rabbit switches achieves clock synchronization better than 50 ps and data throughput sufficient for the LHAASO WCDA detector array.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

This paper presents a data and clock transmission interface prototype for the Water Cherenkov Detector Array component of LHAASO. The design distributes a precise clock and handles high-speed data from 3600 photomultiplier tubes spread over 90,000 square meters using White Rabbit switches over single fibers. Laboratory tests demonstrate clock precision better than 50 picoseconds and data rates up to 400 megabits per second per front-end board. These results support the 0.5 nanosecond RMS timing requirement in a triggerless readout system. The approach simplifies the electronics by combining clock, data, and commands on one fiber while matching the broader LHAASO architecture.

Core claim

The prototype of the data and clock transmission interface achieves a clock synchronization precision better than 50 ps. The data transmission throughput reaches 400 Mbps for one FEE board and 180 Mbps for 4 FEE boards sharing one uplink port in the WR switch, exceeding the requirements of the LHAASO WCDA.

What carries the argument

White Rabbit switches used to transfer clock, data, and commands via a single fiber of about 400 meters.

If this is right

  • Precise clock distribution enables 0.5 ns RMS time measurements across the detector array.
  • High data throughput supports triggerless data acquisition from all PMTs.
  • Single fiber transmission reduces cabling complexity in the large area deployment.
  • The design maintains consistency with other LHAASO readout systems.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Performance in the full 3600-board deployment may differ from lab tests due to increased network load and fiber lengths.
  • This single-fiber synchronization method could apply to other distributed sensor arrays needing high timing precision.
  • TCP/IP protocol integration allows use of standard network tools for data management.

Load-bearing premise

The performance measured in laboratory conditions with single 400 m fiber links and a limited number of boards will hold when the system is scaled to 3600 PMTs and FEEs over the full 90,000 m2 area under actual triggerless data loads.

What would settle it

A measurement showing clock synchronization worse than 50 ps or data throughput below requirements when the full complement of 3600 boards operates with realistic triggerless data traffic over the complete array.

Figures

Figures reproduced from arXiv: 1907.02968 by Cong Ma, Lei Zhao, Qi An, Shaoping Chu, Shubin Liu, Xingshun Gao, Yunfan Yang, Zouyi Jiang.

Figure 1
Figure 1. Figure 1: Layout of the LHAASO complexity. Considering that 3600 PMTs are scattered over a large area of 90000 m2 , to avoid signal attenuation and Signal-to-Noise Ratio (SNR) deterioration caused by signal transmission over long cables, a distributed architecture is proposed for the readout electronics of LHAASO WCDA: 400 FEEs are placed just above water near PMTs, and signal processing and digitization are integra… view at source ↗
Figure 2
Figure 2. Figure 2: Architecture of LHAASO WCDA readout electronics This paper is organized as follows. In Section II, we present the structure of the data and clock transmission interface. In section III, we conducted tests to evaluate its performance. And this paper is concluded in section IV. 2. Architecture [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Structure of the data and clock transmission interface 2.1 Clock Synchronization As shown in figure 4, the clock compensation module consists of two parts: one is the phase adjustment unit and the other is the WRPC that interfaces with the WR switch [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Structure of the clock compensation module [PITH_FULL_IMAGE:figures/full_fig_p005_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Structure of WRPC software running on the CPU [PITH_FULL_IMAGE:figures/full_fig_p006_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Structure of the data transmission interface 2.2.1 Data buffering Both charge and time measurement of the PMT output signals are required in FEE. To achieve a large dynamic range from 1 Photo Electron (P.E.) to 4000 P.E., two channels are used for each PMT: one is used to read out the signal from the anode, and the other is for a dynode. As for time measurement, two thresholds are employed in discriminatio… view at source ↗
Figure 7
Figure 7. Figure 7: Data buffering and commands receiving 2.2.2 SiTCP and Interface Bridge After buffering, the data are sent to the SiTCP, which is a hardware-based TCP processor optimized for the detector systems [11]. The standard TCP/IP communication protocol set is large and complex, and includes management protocols that are not necessary in readout electronics for physics experiments featuring much simpler network. By … view at source ↗
Figure 8
Figure 8. Figure 8: Block diagram of data packaging using SiTCP and WRPC However, SiTCP itself is not compatible with WR protocol. As shown in figure 8, the SiTCP consists of MAC, TCP, ARP/ICMP, UPD and Arbiter blocks. To communicate with the WPRC, an interface bridge is necessary. The SiTCP packages the data, sends it to the WRPC in the “TX” direction, receives data from the WRPC and unpacks it in the “RX” direction. And a … view at source ↗
Figure 9
Figure 9. Figure 9: Structure of Interface Bridge. 2.2.3 Remote Logic Update In the actual application, hundreds of FEEs are scattered over a 90000 m2 area, and these FEEs are places in sealed metal box (four FEEs in each) above the water ponds of WCDA. Therefore, it is very difficult for manual updating of the FPGA logic in FEEs through JTAG (Joint Test Action Group) interfaces after system installation is finished. So the c… view at source ↗
Figure 10
Figure 10. Figure 10: Structure of the remote Logic Update 3. Tests and Results To evaluate the performance of the clock and data transfer interface, we designed a prototype and conducted a series of tests in the laboratory. 3.1 Performance of Clock transmission and Synchronization As mentioned above, high precision clock synchronization is very important for time measurement in LHAASO WCDA. The clock synchronization performan… view at source ↗
Figure 11
Figure 11. Figure 11: Test bench to evaluate the clock compensation performance. As shown in figure 12, the clock phase difference between the data and clock transmission prototype and WR switch is very stable, with a maximum variation of 50 ps. 0 10 20 30 40 50 60 70 Number 2200 2250 2300 2350 2400 2450 2500 skew (ps) range = 47.5 ps RMS = 11.8 ps [PITH_FULL_IMAGE:figures/full_fig_p011_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: Result of clock synchronization test. We also conducted tests to evaluate the performance with varying ambient temperature. As shown in figure 13, we placed one prototype module and the corresponding 400-meter fiber in a climate chamber while the other branches are placed in a constant temperature environment. We implemented FPGA-based Time-to-Digital Converters (TDCs) [16] in these two modules, and used … view at source ↗
Figure 13
Figure 13. Figure 13: Temperature drift test in laboratory. As shown in figure 14, a clock phase compensation precision better than 50 ps is achieved in a temperature range of around 60 °C. [PITH_FULL_IMAGE:figures/full_fig_p012_13.png] view at source ↗
Figure 14
Figure 14. Figure 14: Test result of the compensation precision with varying temperature 3.2 Data Transfer Rate Test We also conducted tests to evaluate the data transfer performance. Data from the prototype module are mixed with the clock signal and transmitted to the WR switch. The data are then extracted by the switch and further sent to a remote PC. Then we can calculate the data transfer rate on the PC, as shown in figure… view at source ↗
Figure 15
Figure 15. Figure 15: Test result of the TCP/IP data transmission Considering that in actual application multiple FEEs will transfer data to one WR switch and further to DAQ, we also conducted tests to evaluate the performance in this situation. In this situation, the data rate is limited not only by the prototype modules but also by the performance of the WR switch. As shown in figure 16, we used four modules connected to one… view at source ↗
Figure 16
Figure 16. Figure 16: Test bench to evaluate the data rate of multiple FEEs with one WR switch [PITH_FULL_IMAGE:figures/full_fig_p013_16.png] view at source ↗
Figure 17
Figure 17. Figure 17: Data rate test result of multiple FEEs with one WR switch 3.3 Data Transfer Integrity Test Based on the handshaking and retransmission mechanism, the TCP/IP protocol itself can guarantee good validity of the data. However, the data checking is based on CRC, which means that only part of the information participates in this checking process. Therefore, there still exists possibility of data errors with sta… view at source ↗
Figure 18
Figure 18. Figure 18: Test bench to evaluate the data integrity [PITH_FULL_IMAGE:figures/full_fig_p014_18.png] view at source ↗
read the original abstract

The Water Cherenkov Detector Array (WCDA) is one of the major components of the Large High Altitude Air Shower Observatory (LHAASO). In the WCDA, 3600 Photomultiplier Tubes (PMTs) and the Front End Electronics (FEEs) are scattered over a 90000 m2 area, while high precision time measurements (0.5 ns RMS) are required in the readout electronics. To meet this requirement, the clock has to be distributed to the FEEs with high precision. Due to the "triggerless" architecture, high speed data transfer is required based on the TCP/IP protocol. To simplify the readout electronics architecture and be consistent with the whole LHAASO readout electronics, the White Rabbit (WR) switches are used to transfer clock, data, and commands via a single fiber of about 400 meters. In this paper, a prototype of data and clock transmission interface for LHAASO WCDA is developed. The performance tests are conducted and the results indicate that the clock synchronization precision of the data and clock transmission is better than 50 ps. The data transmission throughput can reach 400 Mbps for one FEE board and 180 Mbps for 4 FEE boards sharing one up link port in WR switch, which is better than the requirement of the LHAASO WCDA.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The manuscript presents a prototype data and clock transmission interface for the WCDA component of LHAASO. It uses White Rabbit switches to distribute clock, data, and commands over ~400 m single-mode fiber links to FEE boards. Laboratory tests on 1–4 boards are reported to achieve clock synchronization better than 50 ps RMS and throughputs of 400 Mbps (single board) and 180 Mbps (four boards sharing an uplink), stated to exceed WCDA requirements for 0.5 ns RMS timing and triggerless readout of 3600 PMTs over 90 000 m².

Significance. If the reported prototype performance holds under full-scale conditions, the design would provide a compact, fiber-based solution consistent with the rest of LHAASO that simultaneously satisfies the stringent timing and continuous high-rate data-transfer needs of a large water-Cherenkov array. The work directly addresses a practical engineering requirement for the experiment.

major comments (2)
  1. [Abstract / test section] Abstract and test-results section: the central claim that clock synchronization precision is better than 50 ps RMS is stated without any description of the measurement method, reference clock source, calibration procedure, number of samples, or statistical treatment used to obtain the RMS value. This absence prevents independent assessment of the quoted figure.
  2. [Results / performance tests] Results on throughput and synchronization: all reported measurements use only 1–4 FEE boards on single 400 m links. No data, scaling analysis, or simulation are provided for the full 3600-board triggerless load, multi-hop WR topologies, or aggregate traffic that will exist across the 90 000 m² array; the extrapolation from the small prototype therefore remains untested.
minor comments (2)
  1. The manuscript should include a short table or paragraph listing the exact hit-rate assumptions and packet sizes used to calculate the 400 Mbps and 180 Mbps figures.
  2. Figure captions and axis labels for any timing histograms or throughput plots should explicitly state the measurement conditions (fiber length, number of boards, data pattern).

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive comments and the positive assessment of the work's significance. We respond to each major comment below.

read point-by-point responses

  1. Referee: [Abstract / test section] Abstract and test-results section: the central claim that clock synchronization precision is better than 50 ps RMS is stated without any description of the measurement method, reference clock source, calibration procedure, number of samples, or statistical treatment used to obtain the RMS value. This absence prevents independent assessment of the quoted figure.

    Authors: We agree that the abstract and test-results section lack a description of the measurement method, reference clock source, calibration procedure, number of samples, and statistical treatment for the 50 ps RMS figure. Although the performance tests section of the manuscript contains the relevant experimental setup, we will revise the manuscript to add a concise description of these details to the test-results section and update the abstract for clarity. revision: yes

  2. Referee: [Results / performance tests] Results on throughput and synchronization: all reported measurements use only 1–4 FEE boards on single 400 m links. No data, scaling analysis, or simulation are provided for the full 3600-board triggerless load, multi-hop WR topologies, or aggregate traffic that will exist across the 90 000 m² array; the extrapolation from the small prototype therefore remains untested.

    Authors: The manuscript presents prototype results using 1–4 FEE boards, as stated in the test section. We do not provide data, scaling analysis, or simulation for the full 3600-board system or multi-hop topologies. The paper's scope is limited to validating the interface design and per-link performance against WCDA requirements; full-array deployment details are outside this prototype study. We can add a brief discussion of expected scaling based on White Rabbit specifications. revision: partial

Circularity Check

0 steps flagged

No significant circularity: direct hardware measurements

full rationale

The paper reports laboratory test results from a prototype data/clock interface using White Rabbit switches. Performance figures (clock sync <50 ps, throughputs of 400 Mbps and 180 Mbps) are stated as outcomes of direct measurements on 1-4 board setups over 400 m fibers. No equations, fitted parameters, derivations, or self-citations are invoked to obtain these values; they are presented as raw experimental outcomes. The central claims therefore do not reduce to prior inputs by construction and the work is self-contained against external benchmarks.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

No free parameters, invented entities, or ad-hoc axioms are introduced; the work relies on the pre-existing White Rabbit protocol and standard fiber-optic hardware testing practices.

axioms (1)
  • domain assumption White Rabbit switches can distribute clock and data over single-mode fiber with sub-nanosecond precision at the distances and data rates required by WCDA.
    Invoked by the decision to use WR switches for the 400 m links; treated as given from prior WR literature.

pith-pipeline@v0.9.0 · 5796 in / 1094 out tokens · 31184 ms · 2026-05-25T02:00:30.319688+00:00 · methodology

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Reference graph

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