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Investigation of the Power Consumption of the PETsys TOFPET2 ASIC

T0 review · 3 major / 5 minor · reviewed 2026-08-14 · deepseek-v4-flash

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Pith's one-line read The TOFPET2 ASIC's power draw can be predicted from three software settings, ranging from 3.6 to 7.2 mW per channel.

desk verdict Careful ASIC power measurements with a model section that doesn't reproduce as printed—fixable, but equations and Table II need reconciliation. read the letter →

arxiv 1908.05878 v2 pith:JZS2ZOR7 submitted 2019-08-16 physics.ins-det physics.med-ph

Vanessa Nadig , Bjoern Weissler , Harald Radermacher , Volkmar Schulz , David Schug This is my paper · ORCID
classification physics.ins-detphysics.med-ph
keywords TOFPET2ASICpowerconsumptionpositronemissiontomographytime-of-flightPETSiPMreadoutPET/MRcompatibilityapplication-specificintegratedcircuitsanalyticalmodel
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper aims to show that the TOFPET2 readout chip, an application-specific integrated circuit that digitizes silicon-photomultiplier signals in PET detectors, consumes between 3.6 and 7.2 mW per channel depending on three software settings: input-stage impedance, discriminator noise, and discriminator-noise slew rate. It further claims that per-channel power for any configuration can be computed before any experiment by adding independently measured contributions of those three settings to a count-rate-dependent baseline $P_0$. The practical point is that PET electronics inside an MRI scanner must run on low power supplied by linear regulators, since long analog cables degrade timing signals; a chip whose power draw is both low and predictable simplifies future simultaneous PET/MR systems. The same settings also change timing and energy performance, with lower power costing 20 to 40 ps in coincidence resolution time.

What carries the argument

The load-bearing machinery is the linear superposition model of Eq. (4), which splits per-channel power into a baseline $P_0$ and three deltas: $dP_{feib1}$, $dP_{feib2}$, and $dP_{discsfbias}$. The parameters are software settings: fe_ib1 adjusts the input-stage impedance from 11 to 32 ohm, fe_ib2 adjusts a preamplifier current that sets discriminator noise and signal amplification, and disc_sf_bias adjusts the biasing of discriminator signal buffers; increasing any of the three lowers the power draw. Each delta is a least-squares fit of a piecewise linear or parabolic curve to single-parameter scans in which the other two parameters are held at zero. The experimental basis is a shunt-resistor measurement on the 1.2-V low-dropout regulator line, which isolates ASIC operating power from FPGA communication power. The model's defining move is to assert that those single-axis curves continue to hold throughout the three-dimensional parameter space, so a designer can compute the power of an arbitrary configuration triple before running the system.

What would settle it

A targeted grid of two-parameter combinations, e.g., holding fe_ib2=15 and disc_sf_bias=16 while varying fe_ib1, would settle the independence assumption: if measured $P_{ch} - P_0$ differs from the sum of the single-parameter deltas $dP_{feib1}(fe_{ib1}) + dP_{feib2}(15) + dP_{discsfbias}(16)$ by more than the stated ~8% statistical error in a systematic pattern, the additive model fails off the parameter axes.

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Extended reading notes

Core claim

The central claim is that the TOFPET2 ASIC's power consumption is a software-tunable quantity, ranging from 3.6 mW/channel at minimum to 7.2 mW/channel at maximum, and that this variation is described by the additive model $P_{ch} = P_0 + dP_{feib1} + dP_{feib2} + dP_{discsfbias}$ (Eq. 4). Each delta is a piecewise linear or parabolic function of one configuration parameter, fitted to single-parameter scans performed with the other two parameters at zero; $P_0$ is the measured y-intercept at all-zero settings and absorbs count-rate dependence. Validation on random parameter tuples gave a fitted slope of 1.034 ± 0.018 and a negligible intercept of about 0.1 mW/channel, which the authors take as confirmation that the model works for arbitrary configurations. The paper further reports that power is stable across overvoltages from 0.75 V to 7.75 V and across count rates from about 1 kcps to 100,000 kcps, and that reducing power from maximum to minimum worsens coincidence resolution time by 20 to 40 ps while moving the effective photo-electron trigger thresholds.

Load-bearing premise

The load-bearing premise is that fe_ib1, fe_ib2, and disc_sf_bias change power consumption independently, so single-parameter curves measured with the other two at zero remain valid across all combinations; the paper states that cross-parameter interaction experiments were not performed.

Editorial extensions

If this is right

  • A system designer can compute per-channel power draw for any triple of the three settings from the published fit parameters plus one measured baseline, without benchtop measurements per configuration.
  • Choosing the minimum-power configuration (3.6 mW/channel) sacrifices 20 to 40 ps of coincidence resolution time relative to maximum power, while energy resolution changes by less than 0.5% absolute.
  • Because photo-electron trigger levels shift with power setting, threshold calibration (e.g., vth_t1) must be redone after switching between minimum, default, and maximum power configurations.
  • Measured power is stable over count rates from roughly 1 kcps to 100,000 kcps and over overvoltage from 0.75 V to 7.75 V, so the benchmark numbers are representative for realistic operation rather than single-point artifacts.
  • Including the estimated 1.2 mW/channel for ASIC-FPGA communication, the total 4.8 to 8.4 mW/channel remains similar to or below other PET readout ASICs such as Triroc (10 mW/channel), STiC3 (25 mW/channel), and PETA4 (<40 mW/channel).

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • A consequence the authors leave implicit is that the transportability of the fitted single-parameter curves can be established by two-parameter scans; if those scans reproduce the additive predictions, the model becomes a general design rule rather than a validation-set fit.
  • The count-rate dependence sitting entirely in $P_0$ suggests a future circuit-level model that separates digital switching current from analog bias current could predict the baseline analytically and eliminate the one remaining experimental calibration step.
  • The shunt-resistor metrology used here could be reapplied to other ASICs with on-board low-dropout regulators, giving system builders a comparable measure of analog front-end power that excludes FPGA and communication loads.
  • For PET/MR integration, average power is only part of the story: if low-power settings also change the time structure of the current drawn on the 1.2-V line, they could affect electromagnetic interference inside the MR bore in ways the paper does not quantify.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. This paper quantifies the power consumption of the TOFPET2 ASIC as a function of three software-configurable parameters: fe_ib1 (input stage impedance), fe_ib2 (discriminator noise), and disc_sf_bias (discriminator noise slew rate). The authors use a benchtop evaluation kit, measure the 1.2 V supply current via a shunt resistor inserted in place of a fuse on the FEB/D board, and report values from 3.6 to 7.2 mW/channel depending on the configuration. They propose an additive model P_ch = P0 + dP_fe_ib1 + dP_fe_ib2 + dP_disc_sf_bias with piecewise linear/parabolic fits, determine the coefficients by least-squares fits to single-parameter scans, and validate the model on a set of random parameter tuples, reporting a regression slope of 1.034 ± 0.018. They also evaluate coincidence resolution time, energy resolution, filtered count rate, satellite peak fraction, and dark-count trigger level at minimum, default, and maximum power settings, and compare the ASIC with other PET front-end ASICs.

Significance. Provided the analytic model is made reproducible, the paper is a useful engineering contribution: it establishes a tunable power-performance operating range for the TOFPET2 ASIC in a PET/MR context, and the measurement method (current sensing on the LDO input, exclusion of the FPGA line, stability checks over count rate and overvoltage) is carefully described and internally consistent. The comparison table of ASIC power consumptions and the explicit discussion of what the measured power does not include (ASIC-FPGA communication) are valuable. The paper does not claim device-level derivation; it is an empirical model, and the main limitation is that P0 must be measured for each setup and that cross-parameter interactions are not experimentally probed.

major comments (3)
  1. [IV.B, Eq. (6), Table II] Equation (6) defines dP_fe_ib1 using coefficient a3 for the parabolic branch (41 ≤ fe_ib1 ≤ 60), but Table II lists only a0, a1, and a2 and does not contain a3. Table II additionally lists a0, which does not appear in Eq. (6) or in Eq. (7). As printed, the model cannot be evaluated for the upper fe_ib1 range, which includes the default (fe_ib1=59) and minimum (fe_ib1=60) benchmark configurations. The authors should correct the equation/table labels and provide the complete set of coefficients.
  2. [IV.B, Eq. (7), Table II] With the printed values b1 = +2.74×10−3 mW/channel and b2 = +6.70×10−3 mW/channel, dP_fe_ib2 is positive and increasing over fe_ib2 ∈ [21,30]; for example, it is approximately +1.35 mW/channel at fe_ib2=30. This contradicts Fig. 5b, which shows the power consumption decreasing monotonically in fe_ib2, and Table I, which places the minimum power consumption at fe_ib2=30. The equation signs or the table entries are therefore inconsistent, and the model predictions for half of the fe_ib2 range are wrong as printed. This must be reconciled and the corrected model re-validated on the random tuples.
  3. [IV.B, V, and Fig. 6] The claim that the model 'can be used to compute the power consumption prior to experiments' is stronger than what the current evidence supports, because P0 must be measured experimentally for each setup and because the additive superposition of the three single-parameter effects has not been tested for interactions. The random-tuple validation in Fig. 6 is a useful check, but it uses the same setup and the same measurement method as the fits, and the tuple coverage is not reported. The authors should either extend the validation to include interaction-sensitive points (e.g., high fe_ib1 with non-zero fe_ib2 or disc_sf_bias) or explicitly restrict the claim to differential predictions once P0 is known, in the abstract as well as in Section V.
minor comments (5)
  1. [III.A and IV.A] Section III.A states that fe_ib1 was scanned from 0 to 60, yet Section IV.A discusses a 'systematic increase for fe_ib1 > 60' and Fig. 5a marks this with a black circle. Please clarify the actual scan range and what the black circle indicates.
  2. [Fig. 4 caption] The caption says 'KETEK PM3325', but the detector is referred to as 'KETEK PA3325' elsewhere in the text; this should be corrected.
  3. [Eq. (2)] The saturation formula is typeset ambiguously; please define the variables e and s and give the intended mathematical expression for the logarithmic term explicitly.
  4. [IV.B] The 'linearity of 1.034 ± 0.018' is the slope of the measured-versus-computed regression, not a coefficient of determination; the wording should be changed to 'regression slope' for clarity.
  5. [Table II] Table II would be more self-contained if the breakpoints of the piecewise functions (0–40/41–60 for fe_ib1 and 0–20/21–30 for fe_ib2) were included in the caption or as separate columns.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the additive power model is an empirical fit validated on held-out random tuples, and no load-bearing self-citation or definitional reduction is present.

full rationale

The analytical model (Eq. 4) is an explicit empirical ansatz: the dP terms are fit with least squares to one-dimensional parameter sweeps and P0 is measured at the reference tuple, with no claim that the parameters are derived from device physics. The random-tuple validation (Fig. 6) tests the additivity assumption on tuples not used in the fit, so the computed power for those tuples is not identical to the model's inputs by construction. Section V candidly states that P0 must be determined experimentally, that the model has been verified only for the present setup, and that cross-parameter interactions were not probed; these are limitations on the 'prior to experiments' wording rather than circular steps. The mismatch between Eq. (6) and Table II (undefined a3, sign inconsistencies for b1/b2) is a reproducibility/correctness flaw, not circularity. No self-citation is load-bearing and no uniqueness or ansatz is imported from prior work to force the model choice. Therefore the derivation chain is not circular.

Assumptions & free parameters 6 free parameters · 4 assumptions · 0 invented entities

The central power claims rest on a modest set of fitted parameters (model coefficients and P0) and several domain assumptions about the measurement setup and the additivity of parameter effects. No new physical entities are introduced.

free parameters (6)
  • P0 = 7.07 mW/channel (measured)
    Baseline power at fe_ib1=0, fe_ib2=0, disc_sf_bias=0 for the specific setup; must be determined experimentally per setup and absorbs count rate, overvoltage, SiPM type, and scintillator effects.
  • dP_discsfbias slope f0 = (-9.96 ± 0.03) × 10^-3 mW/channel per unit
    Fit to the power versus disc_sf_bias scan in Eq. (5).
  • dP_feib1 coefficients (a0/a1/a2) = a0=(-2.53±0.02)e-3, a1=(-0.60±0.01)e-3, a2=(23.17±1.12)e-3 mW/channel
    Piecewise linear and parabolic fit to the power versus fe_ib1 scan in Eq. (6).
  • dP_feib2 coefficients (b0/b1/b2) = b0=(-45.41±0.17)e-3, b1=(2.74±0.02)e-3, b2=(6.70±0.86)e-3 mW/channel
    Piecewise linear and parabolic fit to the power versus fe_ib2 scan in Eq. (7).
  • Energy calibration factors c and s = Not explicitly listed; fitted to 511 keV and 1274.5 keV peak positions
    Used in Eq. (2) to convert ADC energy values to keV for performance measurements. Not central to the power claim.
  • Bias voltage offset Uoff = Approx. 750 mV per channel
    Used in Eq. (3) to compute the relative offset-corrected overvoltage; determined by probing ASIC channels.
assumptions (4)
  • domain assumption The LDO regulator's quiescent current Iq is negligible, so the average current into the LDO equals the average ASIC supply current IDD12.
    Section III-A; if Iq is not negligible, the measured power would include regulator overhead. The authors state it is negligible but provide no measurement.
  • domain assumption The power contributions of the three configuration parameters are linearly independent and additive across the entire parameter space.
    Section V: 'the introduced model assumes equal behavior of all parts of the ASIC circuit at each point in the three-dimensional parameter space.' This is untested for parameter interactions.
  • domain assumption The power consumption measured on the 1.2 V line excludes ASIC-FPGA communication, and the estimated 1.2 mW/channel overhead from a 30 mA reference on the 2.5 V line is valid.
    Section V; loads on the 2.5 V line cannot be separated from other components, so total power is an estimate rather than a measurement.
  • domain assumption The measured power consumption remains stable across count rates and overvoltages, so benchmark values generalize to the conditions tested.
    Supported by Figs. 7 and 8, but only tested for the given SiPM configurations and setup.

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Cite this review

Pith. "Pith review of Investigation of the Power Consumption of the PETsys TOFPET2 ASIC." pith.science (2026). https://pith.science/paper/JZS2ZOR7

@misc{pith2026190805878,
  author       = {Pith},
  title        = {Pith review of: Investigation of the Power Consumption of the PETsys TOFPET2 ASIC},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/JZS2ZOR7}},
  note         = {Machine review of arXiv:1908.05878}
}
read the original abstract

In state-of-the-art positron emission (PET) tomography systems, application-specific integrated circuits (ASICs)are commonly used to precisely digitize the signals of analog silicon photo-multipliers (SiPMs). However, when operating PET electronics in a magnetic resonance (MR) system, one faces the challenge of mutual interference of these imaging techniques. To prevent signal deterioration along long analog signal lines, PET electronics with a low power consumption digitizing the signals close to the SiPMs are preferred. In this study, we evaluate the power consumption of the TOFPET2 ASIC. Its power consumption ranges from 3.6 to 7.2 mW/channel as a function of the input stage impedance and discriminator noise settings. We present an analytical model allowing to compute the power consumption of a given ASIC configuration. The configured input stage impedance and discriminator noise have an impact on the coincidence resolution time, energy resolution, and photon trigger level. Since the TOFPET2 ASIC delivers state-of-the-art performance with a power consumption similar or even lower than other ASICs typically used for PET applications, it is a favorable candidate to digitize the signals of SiPMs in future simultaneous PET/MR systems.

Figures

Figures reproduced from arXiv: 1908.05878 by the authors.

Figure 1
Figure 1. Benchtop setup included in the TOFPET2 ASIC evaluation kit [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Time difference spectrum of two KETEK PA3325-WB-0808 [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 4
Figure 4. Normalized power consumption on the 1.2-V line accumulated for [PITH_FULL_IMAGE:figures/full_fig_p005_4.png] view at source ↗
Figures from the paper (7 more)
Figure 5
Figure 5. Figure 5: (a) Variation of input stage impedance. (b) Variation of the discriminator noise. (c) Variation of the discriminator noise slew rate. Power consumption [PITH_FULL_IMAGE:figures/full_fig_p006_5.png]
Figure 6
Figure 6. Figure 6: Power consumption at various randomly chosen settings of [PITH_FULL_IMAGE:figures/full_fig_p006_6.png]
Figure 7
Figure 7. Figure 7: Stability of the TOFPET2 ASIC power consumption for changing [PITH_FULL_IMAGE:figures/full_fig_p006_7.png]
Figure 8
Figure 8. Figure 8: Stability of the overvoltage at the three benchmarks of the TOFPET2 [PITH_FULL_IMAGE:figures/full_fig_p007_8.png]
Figure 9
Figure 9. Figure 9: Energy spectra at the three benchmarks: minimum (3.6 mW/channel), default (6.4 mW/channel) and maximum (7.2 mW/channel). Energy spectra were acquired with two KETEK PA3325-WB-0808 SiPM arrays at 4.75 V overvoltage and with vth t1 = 50. Arrows indicate the positions of …
Figure 10
Figure 10. Figure 10: (a) Coincidence resolution time (CRT). (b) Energy resolution [PITH_FULL_IMAGE:figures/full_fig_p007_10.png]
Figure 11
Figure 11. Figure 11: Dark count rate as a function of the first discriminator threshold [PITH_FULL_IMAGE:figures/full_fig_p008_11.png]

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Forward citations

Cited by 1 Pith paper

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  1. PETAT -- An ASIC for Simple and Efficient Readout of Large PET Scanners

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Pith tools

Reviewed August 14, 2026 · model on record in the stance chip above.