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REVIEW 4 major objections 5 minor 6 references

System Evaluation of the Intel Optane Byte-addressable NVM

T0 review · 4 major / 5 minor · reviewed 2026-08-14 · deepseek-v4-flash

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Pith's one-line read Fine-grained DRAM/NVM traffic policies beat DRAM caching by 2x on Intel Optane memory.

desk verdict Useful early look at Optane DC PMM, but the power/efficiency headline claims rest on an unverified assumption about what PCM actually measures. read the letter →

arxiv 1908.06503 v1 pith:TDCDSAJJ submitted 2019-08-18 cs.DC

Ivy B. Peng , Maya B. Gokhale , Eric W. Green This is my paper · ORCID
classification cs.DC
keywords non-volatilememoryIntelOptaneDCpersistentheterogeneousbandwidthspillingwriteisolationpowerefficiencyrooflinemodelNUMA
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper is a measurement study of the first commercially available byte-addressable non-volatile memory, the Intel Optane DC persistent memory module. It argues that on this hardware DRAM should not be treated primarily as a cache for NVM: a fine-grained policy that deliberately spills read traffic between DRAM and NVM delivers roughly 2x the sustained bandwidth and lets applications run about 20% larger problems than DRAM-cached NVM, and a write-isolation policy that keeps write-heavy data in DRAM saves up to 3.9x energy while improving bandwidth by 3.1x. The paper also maps latency, bandwidth, power, and NUMA behavior across eight memory configurations and five graph workloads, and uses a roofline model to show that for data-intensive read traffic NVM draws about 1.8x lower memory power than DRAM. If these results hold, the practical conclusion is that allocator-controlled placement of data across two memory tiers matters more than which tier is designated the cache.

What carries the argument

The central mechanism is a harmonic-sum bandwidth model, $BW_{\mathrm{tot}} = 1/(M_0/BW_0 + (1-M_0)/BW_1)$, with $M_0$ the fraction of traffic sent to DRAM and $BW_0$, $BW_1$ the measured peak DRAM and PMM bandwidths. The model turns the two devices into one aggregate bandwidth pool and directly drives the bandwidth-spilling block allocator, which round-robins blocks across sockets and spills each block from DRAM to NVM after DRAM is exhausted. Its complement is the write-isolation block allocator, which pins write-intensive blocks to DRAM and spreads read-only blocks over both devices through multiple persistent namespaces, avoiding the write-throttling stalls caused by evicting dirty lines from a DRAM cache. Together these policies are what let the paper outperform DRAM-cached NVM, which suffers cache conflicts and dirty-writeback stalls as data grows.

What would settle it

Repeat the STREAM copy and accumulate experiments under write isolation and Memory mode while logging per-DIMM power rails, or run on a socket with DRAM modules removed, and compare dynamic memory energy with the paper's idle-socket subtraction method; the 3.9x energy saving and the 1.8x NVM-vs-DRAM power ratio stand or fall on whether independent metering reproduces them.

Watch

Extended reading notes

Core claim

On the first shipping byte-addressable NVM, the key to performance and energy is not simply which memory is faster, but how traffic is distributed between DRAM and NVM. The paper reports that DRAM-cached NVM (Memory mode) behaves as a direct-mapped write-back cache, and its bandwidth collapses to 5-40 GB/s once data exceeds the DRAM cache. A bandwidth-spilling block allocation that interleaves blocks across sockets and spills each block from DRAM into NVM sustains 76-97 GB/s beyond 1 TB, about 2x the best Memory-mode bandwidth, and pushes the maximum usable data size from 1.28 TB to 1.54 TB. A write-isolation allocation that pins write-intensive blocks to DRAM and read-intensive blocks to NVM sustains 83 GB/s versus 27 GB/s at the largest tested STREAM data size, and cuts energy per gigabyte by up to 3.9x versus Memory mode and 8.4x versus all-PMM. For read-only data-intensive traffic, NVM draws about 1.8x lower memory power than DRAM, although the platform's mandatory DRAM static power keeps total energy dominated by static cost in short runs.

Load-bearing premise

The power and energy conclusions assume that the 38 W memory power measured on an idle socket is also the static power the busy socket would draw, so subtracting it isolates only dynamic memory power.

Editorial extensions

If this is right

  • A workload whose dataset exceeds DRAM capacity can run about 20% larger problems on the same Optane system by using bandwidth spilling instead of DRAM-cached NVM, and can keep roughly 2x the sustained bandwidth past 1 TB.
  • Write isolation turns write-heavy data placement into an energy lever: routing writes to DRAM and reads to NVM cuts energy per gigabyte by up to 3.9x versus Memory mode and 8.4x versus all-PMM in the STREAM copy benchmark, while raising bandwidth from 27 GB/s to 83 GB/s at the largest tested size.
  • Read-heavy traffic should be steered toward NVM: data-intensive reads consume about 1.8x lower memory power from NVM than DRAM, so a roofline-guided distribution can improve both performance and power efficiency.
  • On dual-socket systems, local NVM can beat remote DRAM for read-intensive workloads at high thread counts, so NUMA-aware placement is at least as important as choosing DRAM over NVM.
  • Non-temporal writes to DRAM-cached NVM should be avoided: they cut Memory-mode bandwidth to 47-64% of DRAM's and add about 13% dynamic power, making DRAM-cached NVM less energy-efficient than writing to NVM directly for that access pattern.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Inference: If the 2x bandwidth-spilling gain generalizes beyond this platform, memory allocators should expose DRAM and NVM as parallel bandwidth pools rather than hiding NVM behind a transparent DRAM cache, because the paper's data imply transparent caching leaves most of the aggregate bandwidth unused.
  • Inference: The 1.8x NVM power advantage for read-only traffic suggests power-capped systems could buy compute headroom by moving reads onto NVM; the tradeoff would become much more favorable if future platforms allow idle DRAM DIMMs to be power-gated, since the measured static power of always-on DRAM dominates total energy in short runs.
  • Inference: Equation (1) could be inverted into a closed-loop runtime policy that continuously adjusts the DRAM/NVM split using measured bandwidths and a target energy budget; the paper stops at a static allocation, so a dynamic controller is a natural next step.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 5 minor

Summary. The paper presents a hardware evaluation of the Intel Optane DC persistent memory on a two-socket Purley platform. It measures read/write latency, bandwidth, memory power, and energy under eight memory configurations and then evaluates five graph applications from GAP and Ligra. The second half proposes two fine-grained allocation policies, bandwidth spilling and write isolation, and builds roofline-style performance and power models. The headline claims are that bandwidth spilling provides 2.0x bandwidth and enables 20% larger problems than DRAM-cached NVM, write isolation saves up to 3.9x energy and improves bandwidth by 3.1x, and NVM requires 1.8x lower power than DRAM for data-intensive workloads.

Significance. If these results hold, the paper would be a useful reference for first-generation Optane DC PMM, with directly measured latency and bandwidth data and cross-framework corroboration of graph trends. The harmonic-mean bandwidth model in Eq. (1) is a genuine strength: it is calibrated with measured peak bandwidths (78 GB/s NVM, 204 GB/s DRAM) and then compared with measured policy bandwidths, with no free parameters fitted to the target result. The proposed policies are concrete and falsifiable. The power and energy conclusions, however, rest on measurement assumptions that are currently unvalidated, and the absence of error reporting weakens the quantitative ratio claims.

major comments (4)
  1. [Section 3; Sections 4.3 and 5.3] The paper uses Intel PCM to collect 'power and energy consumption of memory and CPU on each socket' but does not state whether PCM's memory-energy counters include the Optane NVDIMM power domain, namely the media, the Apache Pass controller, the address-indirection cache, and the write-pending logic. This distinction is load-bearing: Figures 6, 8, 15, and 16, together with the abstract's '1.8x lower power' and '3.9x energy saving' claims, are expressed as NVM/DRAM memory power and energy. If PCM reports only the DDR4 DRAM DIMM power, the NVM-side results are systematically understated and the headline comparisons are not valid. Please document the power domain covered by the PCM counters and validate the readings on this platform, for example against a wall-power or board-level measurement.
  2. [Section 4.3, static-power paragraph] The static-power correction is a heuristic and is not validated. The text reports that a socket draws 18-20 W with no application, 38 W when idle while the other socket is busy, and then adopts the 38 W value as the static reference for the busy socket. This assumes that static memory power is identical across sockets and independent of the activities on the busy socket. If that assumption is wrong, the derived dynamic power values in Figure 6, the 4-29x dynamic-power reductions, and the static/dynamic split in Figure 8 would all be distorted. Please validate the static-power reference independently or provide a sensitivity analysis showing that the claimed factors are robust to plausible errors in this baseline.
  3. [Throughout, especially Figures 4, 6, 13, 14, and 15] No repetition counts, error bars, or run-to-run variability are reported for any measured quantity, yet the headline results are ratios of these measurements (2.0x, 3.1x, 3.9x, 1.8x). Without an indication of measurement dispersion, it is impossible for a reader to judge whether the reported differences are significant or stable. Please state the number of repetitions and report representative ranges or confidence intervals for the key comparisons, or explicitly identify which numbers are single-point observations.
  4. [Sections 5.1 and 5.2] The bandwidth-spilling and write-isolation policies are evaluated only with synthetic microbenchmarks (the accumulate kernel and STREAM), not with the GAP or Ligra graph applications studied in Section 4.4. As a result, the paper's broad conclusion that 'applications can significantly optimize performance and power efficiency' through these policies is an extrapolation beyond the measured scope. Please add an end-to-end graph evaluation of the two policies, or explicitly restrict the claim to the microbenchmark workloads.
minor comments (5)
  1. [Figure 7 and caption] The axis label 'Dynaimc Power Efficiency' is a typo for 'Dynamic Power Efficiency'.
  2. [Figure 3] The annotation '~ DRAM 79ns, PMM 174 ns' is placed above both the sequential and random panels, but the text reports different random-access latencies (87 ns and 302 ns); please clarify which label belongs to which panel.
  3. [Figure 16] The heat map in Figure 16 should carry explicit axis labels and units for 'traffic distribution to NVM' and 'arithmetic intensity' rather than relying on the prose to define them.
  4. [Section 4.2, Figure 4] Please add a caption legend that defines the six access patterns, especially the distinction between 'Write' and 'NT-Write'.
  5. [Section 5.1, Figure 13] Please state the exact data points that produce the '2.0x bandwidth' comparison, since the plotted range (76-97 GB/s vs. 40 GB/s) spans a 1.9-2.4x range and the reader cannot reproduce the single ratio.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: bandwidth model is calibrated from independent measurements; power and energy claims are direct measurements.

full rationale

The paper's quantitative claims are not forced by construction. Eq. 1 is a harmonic-mean bandwidth model with BW0 and BW1 taken from independently measured peak bandwidths (204 GB/s DRAM, 78 GB/s NVM on two sockets); the model curve is then compared with measured bandwidth of the spilling policy, so the policy result is not an input to the model. The 2.0x bandwidth and 20% larger problem claims are direct comparisons of measured policy bandwidth against measured Memory-mode bandwidth. Write-isolation energy (up to 3.9x) and bandwidth (3.1x) improvements are measured with PCM and STREAM, not derived from a fitted parameter. The roofline/power-line/arch-line models follow standard definitions from Williams et al. and Choi et al., and the 1.8x lower-power claim is a direct ratio of measured memory power at 100% NVM vs 100% DRAM (54 W vs 95 W). The static-power subtraction (38 W idle-socket reference) is an assumption that could affect dynamic-power magnitudes, and the PCM power-domain coverage of NVDIMMs is a correctness risk, but neither is circular: the subtracted quantity is not derived from the claim. Self-citations [14,22-25] appear only in related work or as suggested optimizations and do not carry the load of any central result. No circular step exists.

Assumptions & free parameters 0 free parameters · 3 assumptions · 0 invented entities

The central claims rest on measured hardware characteristics and two heuristic assumptions: the static-power baseline and the ideal read-bandwidth model. No free parameters are fitted to the target results, and no new physical or abstract entities are introduced. BW0 and BW1 are measured platform peak values, not fitted constants.

assumptions (3)
  • domain assumption The vendor architecture descriptions of Optane DC PMM are accurate: 256-byte media granularity, direct-mapped DRAM cache limited to the same iMC, and write-pending-queue persistence.
    Section 2 describes the platform based on Intel material and prior measurements; the paper does not independently verify these mechanisms, yet they motivate several interpretations of the results.
  • domain assumption Idle-socket memory power of 38 W is a valid static-power baseline for the busy socket.
    Section 4.3 defines dynamic memory power as busy-socket total power minus the idle-socket reference. If static power is not socket-invariant or grows with memory activity, the power and energy claims shift.
  • domain assumption The harmonic bandwidth model in Eq. 1 adequately represents achievable bandwidth for read-only traffic on a DRAM plus NVM system.
    Section 5.1 uses BW0=204 GB/s and BW1=78 GB/s to plot the analytical curve. The model ignores write traffic, cache conflicts, and link contention, and it is validated only on one stream benchmark.

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Cite this review

Pith. "Pith review of System Evaluation of the Intel Optane Byte-addressable NVM." pith.science (2026). https://pith.science/paper/TDCDSAJJ

@misc{pith2026190806503,
  author       = {Pith},
  title        = {Pith review of: System Evaluation of the Intel Optane Byte-addressable NVM},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/TDCDSAJJ}},
  note         = {Machine review of arXiv:1908.06503}
}
abstract

Byte-addressable non-volatile memory (NVM) features high density, DRAM comparable performance, and persistence. These characteristics position NVM as a promising new tier in the memory hierarchy. Nevertheless, NVM has asymmetric read and write performance, and considerably higher write energy than DRAM. Our work provides an in-depth evaluation of the first commercially available byte-addressable NVM -- the Intel Optane DC persistent memory. The first part of our study quantifies the latency, bandwidth, power efficiency, and energy consumption under eight memory configurations. We also evaluate the real impact on in-memory graph processing workloads. Our results show that augmenting NVM with DRAM is essential, and the combination can effectively bridge the performance gap and provide reasonable performance with higher capacity. We also identify NUMA-related performance characteristics for accesses to memory on a remote socket. In the second part, we employ two fine-grained allocation policies to control traffic distribution between DRAM and NVM. Our results show that bandwidth spilling between DRAM and NVM could provide 2.0x bandwidth and enable $20\%$ larger problems than using DRAM as a cache. Also, write isolation between DRAM and NVM could save up to 3.9x energy and improves bandwidth by 3.1x compared to DRAM-cached NVM. We establish a roofline model to explore power and energy efficiency at various distributions of read-only traffic. Our results show that NVM requires 1.8x lower power than DRAM for data-intensive workloads. Overall, applications can significantly optimize performance and power efficiency by adapting traffic distribution to NVM and DRAM through memory configurations and fine-grained policies to fully exploit the new memory device.

Figures

Figures reproduced from arXiv: 1908.06503 by the authors.

Figure 2
Figure 2. The logical view of con"guring all NVDIMMs ei￾ther in App Direct mode or Memory mode. of 128, 256 or 512 GB. Currently, 128-GB NVDIMM has the lowest cost per byte [7]. NVDIMMs use a non-standard DDR-T protocol to enable out-of￾order commands and data transfer to address the long latency to Optane media [7]. In contrast, DRAM DIMMs employ the standard DDR4 protocol. The inset on [PITH_FULL_IMAGE:figures/full_fig_p00… view at source ↗
Figure 3
Figure 3. Latency of sequential and random read accesses to a data bu [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figure 4
Figure 4. Memory bandwidth of mixed read and write sequential accesses on a single socket. One thread per core is used. [PITH_FULL_IMAGE:figures/full_fig_p005_4.png] view at source ↗
Figures from the paper (11 more)
Figure 5
Figure 5. Figure 5: Memory bandwidth on two sockets in Memory [PITH_FULL_IMAGE:figures/full_fig_p006_5.png]
Figure 6
Figure 6. Figure 6: Dynamic memory power of a single socket for six [PITH_FULL_IMAGE:figures/full_fig_p006_6.png]
Figure 7
Figure 7. Figure 7: Dynamic memory power e$ciency calculated as bandwidth per dynamic memory power. presents the sequential read bandwidth in MemoryMode-local con- !guration as the data size increases. The gap between the two op￾tions starts appearing when the data size exceeds the total …
Figure 9
Figure 9. Figure 9: Normalized execution time of "ve graph applications (x-axis) in Ligra and GAP frameworks using four memory con"gurations. Time is normalized to the DRAM con"guration (the red dotted line). Non-temporal writes again signi!cantly impact Memory mode. Without NT-write, the…
Figure 10
Figure 10. Figure 10: Execution time of "ve graph applications with increasing problem size (x-axis) in the GAP graph framework using four memory con"gurations. TC memory footprint exceeds DRAM capacity at s30. s27 s28 s29 s30 s31 0 2 4 6 8 10 12 14 16 18 Normalized Time (x) BFS PMM DRAM-P…
Figure 11
Figure 11. Figure 11: Performance gap between MemoryMode and two PMM con [PITH_FULL_IMAGE:figures/full_fig_p008_11.png]
Figure 12
Figure 12. Figure 12: Normalized execution time using single socket [PITH_FULL_IMAGE:figures/full_fig_p008_12.png]
Figure 13
Figure 13. Figure 13: Compare the bandwidth in App Direct mode using [PITH_FULL_IMAGE:figures/full_fig_p009_13.png]
Figure 14
Figure 14. Figure 14: Compare the bandwidth in App Direct mode using [PITH_FULL_IMAGE:figures/full_fig_p010_14.png]
Figure 15
Figure 15. Figure 15: The total energy on two sockets for each gigabyte [PITH_FULL_IMAGE:figures/full_fig_p010_15.png]
Figure 17
Figure 17. Figure 17: Established models for peak performance and power e [PITH_FULL_IMAGE:figures/full_fig_p011_17.png]

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Reference graph

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