Pith. sign in

REVIEW

A Method for Reducing the Adverse Effects of Stray-Capacitance on Capacitive Sensor Circuits

Not yet reviewed by Pith; the record is open.

This paper has not been read by Pith yet. Machine review is queued; the pith claim, tier, and objections will appear here once it completes.

SPECIMEN: schema-true, not a live event

T0 review · schema-true

One-sentence machine reading of the paper's core claim.

pith:XXXXXXXX · record.json · timestamp

arxiv 1912.07328 v1 pith:BBFUK77L submitted 2019-12-16 physics.ins-det physics.app-ph

classification physics.ins-detphysics.app-ph
keywords noisestray-capacitancecapacitivecircuitssensorvoltageapplicationbenchmark
verification ladder T0 review T1 audit T2 compute T3 formal

Signed reviews

No signed human review yet.

0 comments
read the original abstract

We examine the increase in voltage noise in capacitive sensor circuits due to the stray-capacitance introduced by connecting cables. We have measured and modelled the voltage noise of various standard circuits, and we compare their performance against a benchmark without stray-capacitance that is optimised to have a high signal-to-noise ratio (SNR) for our application. We show that a factor limiting sensitivity is the so-called noise gain, which is not easily avoided. In our application the capacitive sensor is located in a metallic vessel and is therefore shielded to some extent from ambient noise at radio frequencies. It is therefore possible to compromise the shielding of the coaxial connecting cable by effectively electrically floating it. With a cable stray-capacitance of 1.8nF and at a modulation frequency of 100kHz, our circuit has an output voltage noise a factor of 3 larger than the benchmark.

Discussion (0). Continue with ORCID to comment.

Pith tools