Arrow: A RISC-V Vector Accelerator for Machine Learning Inference

Hadi Rayan Al Sandid; Imad Al Assir; Mazen A. R. Saghir; Mohamad El Iskandarani

Arrow: A RISC-V Vector Accelerator for Machine Learning Inference

Not yet reviewed by Pith; the record is open.

Re-run · record.json Download PDF Read on arXiv ↗

This paper has not been read by Pith yet. Machine review is queued; the pith claim, tier, and objections will appear here once it completes.

SPECIMEN: schema-true, not a live event

T0 review · schema-true

One-sentence machine reading of the paper's core claim.

pith:XXXXXXXX · record.json · timestamp

arxiv 2107.07169 v1 pith:X22LYZAI submitted 2021-07-15 cs.AR

Imad Al Assir , Mohamad El Iskandarani , Hadi Rayan Al Sandid , Mazen A. R. Saghir This is my paper

classification cs.AR

keywords arrowinferencelearningmachinevectoracceleratorrisc-vaimed

verification ladder T0 review T1 audit T2 compute T3 formal

0 comments

read the original abstract

In this paper we present Arrow, a configurable hardware accelerator architecture that implements a subset of the RISC-V v0.9 vector ISA extension aimed at edge machine learning inference. Our experimental results show that an Arrow co-processor can execute a suite of vector and matrix benchmarks fundamental to machine learning inference 2 - 78x faster than a scalar RISC processor while consuming 20% - 99% less energy when implemented in a Xilinx XC7A200T-1SBG484C FPGA.

Discussion (0). Sign in to comment.

Forward citations

Cited by 1 Pith paper

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score.

Flexible Vector Integration in Embedded RISC-V SoCs for End to End CNN Inference Acceleration
cs.DC 2025-07 reject novelty 4.0 of 10

Using a Hwacha vector coprocessor, the authors report up to 9x faster image preprocessing and 3x faster fallback execution for YOLOv3 on a NVDLA-based RISC-V SoC, but they mislabel Hwacha as RISC-V Vector 1.0.

Pith tools