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HexaMesh: Scaling to Hundreds of Chiplets with an Optimized Chiplet Arrangement

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arxiv 2211.13989 v4 pith:FJVLIEIL submitted 2022-11-25 cs.AR cs.DCcs.NI

Patrick Iff , Maciej Besta , Matheus Cavalcante , Tim Fischer , Luca Benini , Torsten Hoefler This is my paper · ORCID
classification cs.ARcs.DCcs.NI
keywords arrangementchipletschiplethexameshhigh-performancehundredsicisimproved
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2.5D integration is an important technique to tackle the growing cost of manufacturing chips in advanced technology nodes. This poses the challenge of providing high-performance inter-chiplet interconnects (ICIs). As the number of chiplets grows to tens or hundreds, it becomes infeasible to hand-optimize their arrangement in a way that maximizes the ICI performance. In this paper, we propose HexaMesh, an arrangement of chiplets that outperforms a grid arrangement both in theory (network diameter reduced by 42%; bisection bandwidth improved by 130%) and in practice (latency reduced by 19%; throughput improved by 34%). MexaMesh enables large-scale chiplet designs with high-performance ICIs.

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  1. PlaceIT: Placement-based Inter-Chiplet Interconnect Topologies

    cs.AR 2025-02 conditional novelty 7.0 of 10

    Jointly optimizing chiplet placement and inter-chiplet topology reduces ICI latency by up to 62% for cache-coherent traffic versus a 2D mesh baseline.

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