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Digital Pixel Test Structures implemented in a 65 nm CMOS process

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arxiv 2212.08621 v4 pith:YS5S6GED submitted 2022-12-16 physics.ins-det

classification physics.ins-det
keywords pixelits3alicedetectiondigitaldptsefficiencyfirst
verification ladder T0 review T1 audit T2 compute T3 formal
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abstract

The ALICE ITS3 (Inner Tracking System 3) upgrade project and the CERN EP R&D on monolithic pixel sensors are investigating the feasibility of the Tower Partners Semiconductor Co. 65 nm process for use in the next generation of vertex detectors. The ITS3 aims to employ wafer-scale Monolithic Active Pixel Sensors thinned down to 20 to 40 um and bent to form truly cylindrical half barrels. Among the first critical steps towards the realisation of this detector is to validate the sensor technology through extensive characterisation both in the laboratory and with in-beam measurements. The Digital Pixel Test Structure (DPTS) is one of the prototypes produced in the first sensor submission in this technology and has undergone a systematic measurement campaign whose details are presented in this article. The results confirm the goals of detection efficiency and non-ionising and ionising radiation hardness up to the expected levels for ALICE ITS3 and also demonstrate operation at +20 C and a detection efficiency of 99% for a DPTS irradiated with a dose of $10^{15}$ 1 MeV n$_{\mathrm{eq}}/$cm$^2$. Furthermore, spatial, timing and energy resolutions were measured at various settings and irradiation levels.

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  1. Characterisation of analogue MAPS produced in the 65 nm TPSCo process

    physics.ins-det 2024-11 conditional novelty 5.0 of 10

    CE-65v2 MAPS test structures in 65 nm TPSCo show about 5% gain uniformity, around 1.5 to 2 micrometer spatial resolution at low thresholds, and over 99% efficiency up to roughly 180 electron seed threshold for the Mod...

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