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Sidekick compilation with xDSL

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arxiv 2311.07422 v3 pith:X4JLDLWW submitted 2023-11-13 cs.PL

classification cs.PL
keywords compilerframeworksproductionprototypingsidekickxdslcompilationdevelopment
verification ladder T0 review T1 audit T2 compute T3 formal

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Traditionally, compiler researchers either conduct experiments within an existing production compiler or develop their own prototype compiler; both options come with trade-offs. On one hand, prototyping in a production compiler can be cumbersome, as they are often optimized for program compilation speed at the expense of software simplicity and development speed. On the other hand, the transition from a prototype compiler to production requires significant engineering work. To bridge this gap, we introduce the concept of sidekick compiler frameworks, an approach that uses multiple frameworks that interoperate with each other by leveraging textual interchange formats and declarative descriptions of abstractions. Each such compiler framework is specialized for specific use cases, such as performance or prototyping. Abstractions are by design shared across frameworks, simplifying the transition from prototyping to production. We demonstrate this idea with xDSL, a sidekick for MLIR focused on prototyping and teaching. xDSL interoperates with MLIR through a shared textual IR and the exchange of IRs through an IR Definition Language. The benefits of sidekick compiler frameworks are evaluated by showing on three use cases how xDSL impacts their development: teaching, DSL compilation, and rewrite system prototyping. We also investigate the trade-offs that xDSL offers, and demonstrate how we simplify the transition between frameworks using the IRDL dialect. With sidekick compilation, we envision a future in which engineers minimize the cost of development by choosing a framework built for their immediate needs, and later transitioning to production with minimal overhead.

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Cited by 1 Pith paper

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  1. A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions

    cs.PL 2025-02 conditional novelty 6.0 of 10

    A multi-level MLIR/xDSL backend for the Snitch RISC-V accelerator reaches up to 95% FPU utilization on micro-kernels and 90% when lowered from linalg, without register spilling.

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