Impact of Top SiO2 interlayer Thickness on Memory Window of Si Channel FeFET with TiN/SiO2/Hf0.5Zr0.5O2/SiOx/Si (MIFIS) Gate Structure

Fengbin Tian; Hao Xu; Jia Yang; Junshuai Chai; Mingkai Bai; Runhao Han; Saifei Dai; Shuai Yang; Tao Hu; Tianchun Ye

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Impact of Top SiO2 interlayer Thickness on Memory Window of Si Channel FeFET with TiN/SiO2/Hf0.5Zr0.5O2/SiOx/Si (MIFIS) Gate Structure

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arxiv 2404.15825 v1 pith:QGRNCMQW submitted 2024-04-24 physics.app-ph

Tao Hu , Xianzhou Shao , Mingkai Bai , Xinpei Jia , Saifei Dai , Xiaoqing Sun , Runhao Han , Jia Yang

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Xiaoyu Ke Fengbin Tian Shuai Yang Junshuai Chai Hao Xu Xiaolei Wang Wenwu Wang Tianchun Ye

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classification physics.app-ph

keywords sio2memorywindowchannelfefetgateimpactinterlayer

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We study the impact of top SiO2 interlayer thickness on memory window of Si channel FeFET with TiN/SiO2/Hf0.5Zr0.5O2/SiOx/Si (MIFIS) gate structure. The memory window increases with thicker top SiO2. We realize the memory window of 6.3 V for 3.4 nm top SiO2. Moreover, we find that the endurance characteristic degrades with increasing the initial memory window.

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