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arxiv: 2405.13170 · v1 · submitted 2024-05-21 · 💻 cs.AR

FEATHER: A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching

Jianming Tong , Anirudh Itagi , Prasanth Chatarasi , Tushar Krishna This is my paper

Pith reviewed 2026-05-24 01:08 UTC · model grok-4.3

classification 💻 cs.AR
keywords reconfigurable acceleratordataflow switchingon-chip data reorderingML inferenceNest spatial arrayBIRRD reduction networkFPGA deploymentdata layout optimization
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The pith

FEATHER accelerator uses Nest array and BIRRD network to reorder data on-chip for seamless per-layer dataflow switches at low cost.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper aims to show that ML accelerators can switch to the optimal dataflow for each layer without the usual high overhead of data layout reordering and datapath changes. It introduces a spatial array called Nest and a multi-stage reduction network called BIRRD that embed reordering and flexible reduction into the hardware itself. This design is modeled in an enhanced version of Timeloop called Layoutloop and implemented on FPGA hardware. Results indicate latency and energy gains over fixed and other reconfigurable accelerators while adding only modest area. The core idea is that on-chip support for reordering removes the barrier to using diverse dataflows.

Core claim

FEATHER leverages a novel spatial array termed Nest and a novel multi-stage reduction network called BIRRD for performing flexible data reduction with layout reordering under the hood, enabling seamless switching between optimal dataflows with negligible latency and resources overhead.

What carries the argument

Nest spatial array combined with BIRRD multi-stage reduction network, which integrate data layout reordering into computation and reduction steps.

If this is right

  • Each layer of a model can run under its own best dataflow without paying a reconfiguration penalty each time.
  • Inference latency improves by 1.27 to 2.89 times and energy efficiency by 1.3 to 6.43 times versus prior accelerators.
  • FPGA throughput rises 2.65 to 3.91 times over Xilinx DPU and Gemmini while using only 6 percent extra area over a fixed-dataflow baseline.
  • The Layoutloop extension allows systematic comparison of dataflow choices that also account for layout costs.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Designers of future edge accelerators could adopt the same embedded reordering approach instead of building separate fixed units for each dataflow.
  • The low-overhead switching might allow runtime adaptation of dataflows based on changing workload or power constraints.
  • Extending the same mechanism to larger chips or multi-chip systems could reduce the need for complex off-chip data movement during model execution.

Load-bearing premise

The Nest array and BIRRD network can handle every required data reordering and reconfiguration for any dataflow with negligible added latency and area.

What would settle it

Direct measurement on the FPGA implementation showing reordering latency or area overhead rising sharply for a dataflow switch not covered in the reported ResNet-50 and MobileNet-V3 cases.

Figures

Figures reproduced from arXiv: 2405.13170 by Anirudh Itagi, Jianming Tong, Prasanth Chatarasi, Tushar Krishna.

Figure 1
Figure 1. Figure 1: Terminology of convolution workload and dataflow [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Latency evaluation of dataflows on 16×16 PE array with various layouts (error bar shows layout impacts, less latency is better). The best flexible dataflow (green bar) theoretically reduces overall latency of fixed dataflow-layout (blue bar) by 63.3%. However, ignoring the impact of layout considerations in theoretical dataflows results in up to a 128× latency gap in practice (yellow bar). FEATHER eliminat… view at source ↗
Figure 3
Figure 3. Figure 3: Layout terminology example: ‘CHW W4H2C2’. ‘CHW’ signifies the inter-line dimension order as C→H→W across lines. ‘W4H2C2’ indicates the intra-line dimension order: (4,2,2) elements from the (W,H,C) dimensions are flattened into a single row in the order of W→H→C. words a buffer could supply per cycle) and the depth represents the total number of buffer row entries as shown in [PITH_FULL_IMAGE:figures/full_… view at source ↗
Figure 4
Figure 4. Figure 4: Memory efficiency and computation utilization of various [PITH_FULL_IMAGE:figures/full_fig_p004_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Overview of reordering patterns. The 2D layout without any reordering is shown in 5a, which only allows reading two rows concurrently, assuming true dual-port SRAM. Line Rotation (5b, e.g., Medusa [48]) moves a row from bank 0 to bank 1 prior to reading, enabling simultaneous access to at most three rows from bank 0 through dual-bank ports. This technique, however, utilizes additional port from bank 1, pot… view at source ↗
Figure 6
Figure 6. Figure 6: Comparison of data reordering implementations. This work proposes RIR that eliminates reorder latency and bank conflicts. We discuss on-chip reorder patterns, including transpose, line rotation, row-reorder and arbitrary reorder, in [PITH_FULL_IMAGE:figures/full_fig_p005_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: Overview of FEATHER architecture. The compute pipeline (NEST→BIRRD→OB→QM) reads iActs from StaB Ping (or Pong) and writes oActs to StaB Pong (or Ping) with a new data layout. (§IV), (iii) a tool called LayoutLoop for dataflow and layout co-exploration (§V). FEATHER provides two specific benefits over prior work in data reordering: (i) supporting arbitrary reorder, and (ii) proposing RIR to hide reordering … view at source ↗
Figure 8
Figure 8. Figure 8: Micro-architecture of FEATHER’s datapath for convo￾lution/GEMM. For convolution, the NEST reads iActs from StaB and weights from StrB, streaming both in a top-to-bottom pipeline. PEs in a column time-multiplex a common output bus. BIRRD conducts global spatial reduction and reorders results for targeted StaB banks during reduction, altering data layout in StaB. NEST facilitates inter-layer pipelining by re… view at source ↗
Figure 9
Figure 9. Figure 9: Illustration of the FEATHER with NEST and BIRRD employing a convolutional operation with a 2×2 weights featuring 2 input channels (C = 2) and generating 16 output channels (M = 16) across a 4×4 iAct with 2 input channels. The depicted dataflow utilizes a weight-stationary approach, where each PE has a local register file containing a channel of weights (2×2). The dataflow is parallelized for two input chan… view at source ↗
Figure 10
Figure 10. Figure 10: Comparison between per-layer flexible dataflows in [PITH_FULL_IMAGE:figures/full_fig_p009_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: Example of FEATHER switching from channel-last lay￾out (HWC C4) to a row-major format (MPQ Q4(CHW W4)) during reduction without incurring bank conflicts. This is because multiple iActs are reduced into fewer oActs, thereby reducing accesses within each bank. In this example, NEST leverages parallelism along the kernel M and channel C dimensions, reading and vertically streaming four iActs of four input ch… view at source ↗
Figure 12
Figure 12. Figure 12: FEATHER vs. SoTAs on real devices. We run each [PITH_FULL_IMAGE:figures/full_fig_p011_12.png] view at source ↗
Figure 13
Figure 13. Figure 13: FEATHER vs. SoTA using Layoutloop (Percentage inside each blue bar indicates average steady-state PE utilization. Red bar indicates bank conflict slowdown, while yellow bar indicates off-chip reordering costs. Lower is better. (The red text in the x-axis of the right chart mentions the fixed layout or the layout reordering mechanism for each design.) With per-layer dataflow-layout switching, FEATHER achie… view at source ↗
Figure 14
Figure 14. Figure 14: ASIC resource comparison (FEATHER vs. SoTA). 16×16 FEATHER place-and-route at TSMC 28nm. E. Timing Analysis We layout FEATHER with 64, 256, and 1024 PEs, requiring BIRRD with 8, 16, and 32 inputs. The die photo of FEATHER with 16×16 PEs is shown in Fig. 14b revealing that BIRRD consumes only 4% of the overall post-layout area in the TSMC 28nm process. BIRRD does not have long wires because it is placed ou… view at source ↗
read the original abstract

The inference of ML models composed of diverse structures, types, and sizes boils down to the execution of different dataflows (i.e. different tiling, ordering, parallelism, and shapes). Using the optimal dataflow for every layer of workload can reduce latency by up to two orders of magnitude over a suboptimal dataflow. Unfortunately, reconfiguring hardware for different dataflows involves on-chip data layout reordering and datapath reconfigurations, leading to non-trivial overhead that hinders ML accelerators from exploiting different dataflows, resulting in suboptimal performance. To address this challenge, we propose FEATHER, an innovative accelerator that leverages a novel spatial array termed Nest and a novel multi-stage reduction network called BIRRD for performing flexible data reduction with layout reordering under the hood, enabling seamless switching between optimal dataflows with negligible latency and resources overhead. For systematically evaluating the performance interaction between dataflows and layouts, we enhance Timeloop, a state-of-the-art dataflow cost modeling and search framework, with layout assessment capabilities, and term it as Layoutloop. We model FEATHER into Layoutloop and also deploy FEATHER end-to-end on the edge ZCU104 FPGA. FEATHER delivers 1.27~2.89x inference latency speedup and 1.3~6.43x energy efficiency improvement compared to various SoTAs like NVDLA, SIGMA and Eyeriss under ResNet-50 and MobiletNet-V3 in Layoutloop. On practical FPGA devices, FEATHER achieves 2.65/3.91x higher throughput than Xilinx DPU/Gemmini. Remarkably, such performance and energy efficiency enhancements come at only 6% area over a fixed-dataflow Eyeriss-like accelerator. Our code is released at https://github.com/maeri-project/FEATHER.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The manuscript presents FEATHER, a reconfigurable accelerator for ML inference that uses a novel Nest spatial array and BIRRD multi-stage reduction network to support flexible data layout reordering and datapath reconfiguration. This is claimed to enable seamless switching between optimal dataflows (tiling, ordering, parallelism, shapes) with negligible latency and resource overhead. The authors enhance Timeloop into Layoutloop for joint dataflow-layout modeling, evaluate FEATHER in simulation against NVDLA/SIGMA/Eyeriss baselines on ResNet-50 and MobileNet-V3, and deploy it on a ZCU104 FPGA where it achieves 2.65/3.91x throughput over Xilinx DPU/Gemmini at 6% area overhead relative to a fixed-dataflow Eyeriss-like design. Code is released.

Significance. If the negligible-overhead claim for arbitrary dataflow switching holds, the work could enable more adaptive accelerators that exploit per-layer optimal dataflows without the usual reconfiguration penalty, improving latency and energy on edge devices. Positive elements include the end-to-end FPGA implementation, public code release for reproducibility, and the Layoutloop extension for systematic evaluation. The reported speedups (1.27-2.89x latency, 1.3-6.43x energy) and low area cost would be impactful if the core hardware mechanisms are shown to generalize beyond the evaluated workloads.

major comments (2)
  1. [Evaluation sections (Layoutloop modeling and FPGA deployment)] The central claim that Nest and BIRRD perform all required layout reordering and datapath reconfiguration with negligible latency/resource overhead for arbitrary dataflows (stated in the abstract) is load-bearing but unsupported by isolated measurements. Only aggregate results for ResNet-50 and MobileNet-V3 layers are reported in Layoutloop and the ZCU104 deployment; no breakdown isolates reconfiguration cycles, extra BRAM/DSP usage, or latency scaling when switching between non-evaluated tilings, orderings, or shapes.
  2. [Nest and BIRRD architecture description] The assumption that the reordering network's latency remains negligible independent of dataflow complexity is not tested. If BIRRD latency scales with reduction complexity (common in multi-stage networks), the headline speedups become workload-specific rather than general, undermining the 'seamless switching' contribution.
minor comments (2)
  1. [Abstract] Abstract contains a typo: 'MobiletNet-V3' should be 'MobileNet-V3'.
  2. [Evaluation methodology] The manuscript lacks visible error bars, full methodology details on post-hoc design choices, or discussion of how Layoutloop models reconfiguration costs, reducing verifiability of the reported speedups.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive feedback. We address each major comment below with clarifications drawn from the manuscript and indicate revisions to strengthen the evidence for our claims.

read point-by-point responses

  1. Referee: [Evaluation sections (Layoutloop modeling and FPGA deployment)] The central claim that Nest and BIRRD perform all required layout reordering and datapath reconfiguration with negligible latency/resource overhead for arbitrary dataflows (stated in the abstract) is load-bearing but unsupported by isolated measurements. Only aggregate results for ResNet-50 and MobileNet-V3 layers are reported in Layoutloop and the ZCU104 deployment; no breakdown isolates reconfiguration cycles, extra BRAM/DSP usage, or latency scaling when switching between non-evaluated tilings, orderings, or shapes.

    Authors: The manuscript reports aggregate end-to-end results because these reflect realistic ML workloads, with the FPGA deployment on ZCU104 capturing all overheads in practice (yielding the reported throughput gains at 6% area). The architecture sections describe how Nest and BIRRD fuse reordering into the reduction path without extra cycles or dedicated resources. We agree that isolated breakdowns would make the negligible-overhead claim more explicit and will add a new microbenchmark subsection with reconfiguration cycle counts, BRAM/DSP deltas, and scaling across varied tilings and shapes in the revision. revision: yes

  2. Referee: [Nest and BIRRD architecture description] The assumption that the reordering network's latency remains negligible independent of dataflow complexity is not tested. If BIRRD latency scales with reduction complexity (common in multi-stage networks), the headline speedups become workload-specific rather than general, undermining the 'seamless switching' contribution.

    Authors: BIRRD uses a fixed number of pipeline stages whose depth is independent of dataflow parameters; reordering is offloaded to the spatial connections in Nest rather than increasing network stages. This bound is implicit in the consistent low-overhead results across the diverse layers of the two evaluated networks and the FPGA measurements. We will expand the architecture description with an explicit latency analysis showing the fixed-stage property to address the concern. revision: partial

Circularity Check

0 steps flagged

No significant circularity; claims rest on new hardware and external empirical evaluation

full rationale

The paper introduces Nest and BIRRD as novel components enabling data reordering and reconfiguration, then evaluates them via an enhanced Timeloop (Layoutloop) model and ZCU104 FPGA deployment. Performance numbers (1.27-2.89x latency, etc.) are reported as direct comparisons to external baselines (NVDLA, SIGMA, Eyeriss, Xilinx DPU, Gemmini). No equations, fitted parameters, or self-citations are shown that reduce any prediction or result to the inputs by construction. The 'negligible overhead' premise is an engineering claim supported by aggregate measurements rather than a self-referential derivation. This is a standard non-circular hardware design paper.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 2 invented entities

Abstract-only review provides limited visibility into modeling assumptions; the central claim rests on the functional correctness and low-overhead behavior of the two newly introduced hardware blocks (Nest and BIRRD) whose independent validation is the FPGA results.

invented entities (2)
  • Nest no independent evidence
    purpose: spatial array enabling flexible data handling and reordering
    New component proposed to support dataflow switching
  • BIRRD no independent evidence
    purpose: multi-stage reduction network that performs data reduction together with layout reordering
    New component proposed to hide reordering overhead

pith-pipeline@v0.9.0 · 5880 in / 1505 out tokens · 29907 ms · 2026-05-24T01:08:00.715237+00:00 · methodology

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