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REVIEW 3 major objections 3 minor 95 references

EDM: An Ultra-Low Latency Ethernet Fabric for Memory Disaggregation

T0 review · 3 major / 3 minor · reviewed 2026-08-12 · deepseek-v4-flash

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Pith's one-line read EDM claims that moving the remote-memory protocol stack into the Ethernet PHY and adding a centralized in-switch scheduler cuts remote read and write latency to roughly 300 ns, beating RoCEv2 and TCP/IP by an order of magnitude and…

desk verdict Solid FPGA demonstration of a sub-300ns in-PHY memory fabric, but the high-load latency claims rest on a simulator with inconsistent parameters. read the letter →

arxiv 2411.08300 v4 pith:HWICA5OG submitted 2024-11-13 cs.OS cs.NI

Weigao Su , Vishal Shrivastav This is my paper · ORCID
classification cs.OScs.NI
keywords memorydisaggregationEthernetPHYremotelatencyin-networkschedulerparalleliterativematchingvirtualcircuitsFPGAprototypesmall-messagetransport
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

EDM sets out to make Ethernet a practical fabric for memory disaggregation by attacking the two biggest sources of remote-access latency: the host protocol stack and the switch. Its first move is radical: instead of layering RDMA or TCP/IP on top of the Ethernet MAC, EDM puts the entire remote-memory protocol inside the Physical Coding Sublayer (PCS), where data moves in 66-bit blocks and idle gaps can carry memory traffic. Its second move is to place a centralized scheduler inside the switch PHY that grants bandwidth in the form of short virtual circuits, so memory messages never queue or wait for layer-2 processing. On an FPGA testbed, the paper reports fabric latency of roughly 300 ns for remote reads and writes, which is 3.7 to 12.7 times lower than raw Ethernet, RoCEv2, and hardware TCP/IP, and comparable to CXL. Simulations at 144 nodes keep average latency within 1.3 times the unloaded value even at high load, which matters because it suggests remote memory over commodity Ethernet could escape the congestion collapse that plagues small-message traffic.

What carries the argument

The load-bearing machinery is the Ethernet Physical Coding Sublayer (PCS), the part of the PHY that encodes data into 66-bit blocks, repurposed as the data path for memory messages via new /M*/, /N/, and /G/ block types. On the switch, the key mechanism is a centralized scheduler that implements priority-based Parallel Iterative Matching (PIM), the classic switch-scheduling algorithm that matches inputs to outputs iteratively, extended so each iteration takes a constant three clock cycles through ordered-list hardware and a priority encoder. The scheduler's grants create virtual circuits in the PHY between source and destination ports, which is what eliminates queuing, drops, and layer-2 forwarding at the switch for memory traffic.

What would settle it

Build or simulate a 512-port EDM switch at the claimed 3 GHz clock and measure whether a maximal matching is actually formed in about 27 cycles; if the matching latency exceeds the transmission time of the 128-byte or 256-byte chunk, the zero-queuing promise fails on the first incast, and average latency under 80 percent all-to-all load will exceed the claimed 1.3 times unloaded.

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Extended reading notes

Core claim

The central claim is that the Ethernet MAC layer is not an unavoidable price of using Ethernet for remote memory access. By operating directly in the Physical Coding Sublayer, EDM carries memory messages as custom 66-bit PHY block types, reuses inter-frame gap bits, and achieves intra-frame preemption at 66-bit granularity, eliminating the 64-byte minimum frame, the IFG overhead, and head-of-line blocking caused by large non-memory frames. The companion claim is that a centralized scheduler implemented in the switch PHY can form a priority-based online maximal matching fast enough to reserve bandwidth in advance, so memory traffic is forwarded through virtual circuits with zero queuing and zero layer-2 processing delay. On the testbed, remote reads and writes complete through the fabric in about 300 ns, and in simulation the average completion time stays within 1.2 to 1.4 times the ideal for several disaggregated application workloads, outperforming reactive transports and CXL-style credit flow control under load.

Load-bearing premise

The scheduler's zero-queuing and high-utilization guarantees depend on it forming a maximal matching in about 3 times log(N) clock cycles at a clock rate fast enough that the chosen chunk size keeps every link busy; if computing the matching takes longer than sending a chunk, links go idle and queues build.

Editorial extensions

If this is right

  • If EDM's numbers hold, remote memory reads and writes over Ethernet can run at latencies previously associated with PCIe-attached CXL, so memory disaggregation does not require a separate fabric.
  • Memory traffic can share links with IP and storage traffic without sacrificing small-message latency, because 66-bit-granularity preemption bounds interference from large frames.
  • Removing the TCP/IP or RDMA transport stack from the memory data path eliminates per-packet encapsulation and congestion-control delays, simplifying the host NIC for memory traffic.
  • With a scheduler guaranteeing zero queuing, applications see predictable memory-access latency even under incast-like many-to-one loads.
  • The ASIC synthesis suggests the scheduler fits within a modern switch chip: roughly 10 mm2 of area and about 1 MB of SRAM for a 512-port switch, which is a concrete scaling path beyond the two-port FPGA prototype.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • A testable extension the paper does not explore is whether the same PHY-level multiplexing can carry other latency-critical traffic, such as coherence or synchronization primitives, alongside memory and IP traffic; only memory messages and grants are defined.
  • The paper fixes a 256-byte chunk and a 2.56 ns clock in the testbed; at higher line rates the zero-queuing guarantee would require either faster matching or larger chunks, and the latency cost of larger chunks for tiny 8-byte read requests is not quantified.
  • Because one-sided writes pay a notification-and-grant round trip before sending data, a workload dominated by small one-sided writes would stress whether that RTT/2 overhead stays negligible in practice.
  • A consequence the authors leave implicit is that a working EDM at scale would undercut the main argument for deploying CXL or InfiniBand purely for memory pooling, since Ethernet already exists in every rack and would also carry the disaggregated memory traffic.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 3 minor

Summary. The paper proposes EDM, an Ethernet fabric for memory disaggregation that moves the remote-memory protocol stack into the Physical Coding Sublayer of the Ethernet PHY and adds a centralized, in-PHY scheduler at the switch. The scheduler builds a priority-based online maximal matching and creates PHY-level virtual circuits, with the goal of eliminating queuing, layer-2 forwarding, and transport-stack latency for memory traffic. The paper reports an unloaded remote read/write fabric latency of roughly 300 ns on an FPGA testbed, claims this is 3.7--12.7x lower than raw Ethernet, RoCEv2, and hardware TCP/IP, and uses a C network simulator to claim that under high load the average latency stays within 1.3x the unloaded value and that average message completion times are within 1.2--1.4x of ideal for several disaggregated workloads.

Significance. The unloaded-latency result is a substantial empirical contribution: it is measured on an FPGA testbed, backed by a detailed cycle-level breakdown in Table 1 and Figure 5, and accompanied by a public Verilog artifact. The idea of implementing remote memory access in the PHY, with custom 66-bit block types and intra-frame preemption, is novel and potentially impactful for memory disaggregation. The centralized in-PHY scheduler is also a well-motivated design point. The high-load claim, however, is the main reason the paper's central latency story generalizes beyond the unloaded case, and that claim currently rests on a simulator parameterization that is internally inconsistent with the scheduler timing model. The high-load result therefore needs to be re-established with a consistent set of parameters before the paper's conclusions are fully supported.

major comments (3)
  1. [§4.3, with §3.1.2 and §3.1.3] The simulator in §4.3 uses a 256 B chunk at 100 Gbps with N=144 nodes, but it never states the scheduler clock. If the simulator inherits the 2.56 ns testbed clock used in Figure 5, then forming a maximal matching takes 3·log2(144) ≈ 21.5 cycles, or about 55 ns, while a 256 B chunk on a 100 Gbps link transmits in 20.5 ns. This violates the line-rate condition derived in §3.1.3, which requires the chunk transmission time to be at least the matching latency to keep links busy. Under the 2.56 ns clock the per-port throughput would be capped near 256 B / 55 ns ≈ 4.7 Gbps, not 100 Gbps, so the 1.3x high-load latency figure is not supported by the stated parameters. If instead the scheduler runs at the 3 GHz ASIC clock of §4.1, the 256 B chunk is viable, but then the simulator does not match the testbed timing used elsewhere in §4.3. Please state the scheduler clock explicitly and rerun with a consistent chunk/clock combination, e.g., a 688 B chunk at 2.56 ns, or 256 B with the 3 GHz ASIC scheduler.
  2. [Figure 8 caption / inserted note] The manuscript itself admits a second simulator defect: read flows are initialized with 8 B RREQs, but the load accounting uses the 64 B RRES size, so the reported network load overstates the real injected traffic. The statement that this factor 'can be offsetted by real workloads' is not quantified and is not a substitute for correct load accounting. Because Figure 8a and the application MCT results in Figure 8b are the evidence for the high-load latency claim, the load definition must be corrected and the simulations repeated before the 1.3x claim can be accepted.
  3. [§4.2.1] The text states that 'testbed experiments showed that even under interference from IP traffic, EDM maintained a near-constant ~300 ns remote memory access latency,' but no such experiment, figure, or measurement procedure is presented in §4.2. Either the data should be reported, or the claim should be removed or explicitly labeled as a qualitative observation.
minor comments (3)
  1. [Figure 8] The inserted note about RREQ/RRES size accounting is written in informal, ungrammatical prose ('offsetted') and should be moved into the methodology section as a clearly stated assumption or limitation.
  2. [§4.2.2] The paper refers to a 'cycle-accurate FPGA hardware simulator' for the YCSB evaluation; please clarify whether this simulator is the same implementation as the testbed, and how its timing parameters were derived.
  3. [References] Reference [49] (Scale-out NUMA) appears to be duplicated as [50]; the duplicate should be removed and subsequent citations renumbered.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: unloaded latency is measured, high-load behavior is simulated from the design, and self-citations are non-load-bearing building blocks.

full rationale

The paper's central latency result (~300 ns) is a direct FPGA measurement from an implemented testbed (Table 1, Figure 5), not a fitted or self-referential prediction. The high-load result (within 1.3x unloaded) comes from a C network simulator that implements the scheduler's grant algorithm; the zero-queuing property is a design invariant of maximal matching, not an empirical claim derived from itself. Empirical parameter choices (X=3, chunk size 256B) are simulator settings, not parameters fitted to the reported target metric. Citations to prior PHY idle-block work [36,37,39,60,91] and to constant-time ordered-list hardware structures [57-59,63] include the authors' own papers, but the EDM implementation and ASIC synthesis provide independent support; these citations are building blocks, not unverified premises that force the conclusion. The Figure 8 note admitting that read flows use 8B RREQs while load is accounted at 64B RRES, and the possible mismatch between scheduler matching latency and chunk transmission time, are correctness/consistency risks, not circular derivations. No step in the derivation chain equates an output to an input by construction.

Assumptions & free parameters 3 free parameters · 4 assumptions · 2 invented entities

The paper's performance claims rest on three fitted or assumed quantities: the chunk size, the maximum active notifications per source-destination pair, and the scheduler clock rate. The PHY-injection mechanism assumes prior PHY-idle manipulation results, and the reliability model assumes corruption is permanent. The invented block types and virtual circuits are internal to the design and have no external evidence beyond the prototype.

free parameters (3)
  • chunk_size_c = 256 B in simulations; 128 B for line-rate 512-port estimate
    Chunk size is a scheduler parameter that must exceed the matching latency times the link rate; 256 B is used in section 4.3 without demonstrating that the line-rate condition holds at the testbed clock.
  • max_active_notifications_X = 3
    Set to 3 as empirically found best in section 3.1.2; it bounds the per-destination notification queue and serializes outstanding messages per source-destination pair.
  • scheduler_clock_rate = 3 GHz (ASIC estimate)
    Used to claim 9 ns matching latency for a 512-port switch; the FPGA prototype runs at a 2.56 ns clock, so the ASIC clock is an unvalidated estimate.
assumptions (4)
  • domain assumption The Ethernet PCS interface between encoder and scrambler permits insertion of custom 66-bit block types and reuse of idle blocks without breaking clock recovery or scrambling.
    Invoked in section 3.2 to place EDM logic in the PCS; relies on prior PHY-channel work [36,37,60,91].
  • domain assumption Memory traffic demand is known in advance: read sizes are available from RREQ and write sizes from explicit notifications.
    Used in section 3.1.1 to build the demand notification queue; depends on the memory controller interface exposing request sizes.
  • ad hoc to paper Link data corruption is non-transient and can be handled by disabling the link rather than retransmission.
    Stated in section 3.3; EDM provides no end-to-end reliability for memory messages, which is a significant departure from transport expectations.
  • domain assumption A single switch with hundreds of ports is the target topology; multi-hop fabrics are out of scope.
    Stated in section 2.1; the scheduler creates virtual circuits within one switch and fault tolerance assumes a backup top-of-rack switch.
invented entities (2)
  • /M*/, /N/, and /G/ 66-bit PHY block types
    purpose: Carry memory messages, demand notifications, and grants inside the PCS; distinguish memory traffic from standard Ethernet blocks.
    These block types are defined by the paper and demonstrated only in the paper's own FPGA prototype; no external implementation or standard supports them.
  • In-PHY virtual circuits
    purpose: Forward memory data between matched source and destination ports without layer 2 processing.
    A logical construct of the scheduler; its properties are argued from the matching algorithm rather than independently measured.

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Cite this review

Pith. "Pith review of EDM: An Ultra-Low Latency Ethernet Fabric for Memory Disaggregation." pith.science (2026). https://pith.science/paper/HWICA5OG

@misc{pith2026241108300,
  author       = {Pith},
  title        = {Pith review of: EDM: An Ultra-Low Latency Ethernet Fabric for Memory Disaggregation},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/HWICA5OG}},
  note         = {Machine review of arXiv:2411.08300}
}
abstract

Achieving low remote memory access latency remains the primary challenge in realizing memory disaggregation over Ethernet within the datacenters. We present EDM that attempts to overcome this challenge using two key ideas. First, while existing network protocols for remote memory access over the Ethernet, such as TCP/IP and RDMA, are implemented on top of the MAC layer, EDM takes a radical approach by implementing the entire network protocol stack for remote memory access within the Physical layer (PHY) of the Ethernet. This overcomes fundamental latency and bandwidth overheads imposed by the MAC layer, especially for small memory messages. Second, EDM implements a centralized, fast, in-network scheduler for memory traffic within the PHY of the Ethernet switch. Inspired by the classic Parallel Iterative Matching (PIM) algorithm, the scheduler dynamically reserves bandwidth between compute and memory nodes by creating virtual circuits in the PHY, thus eliminating queuing delay and layer 2 packet processing delay at the switch for memory traffic, while maintaining high bandwidth utilization. Our FPGA testbed demonstrates that EDM's network fabric incurs a latency of only $\sim$300 ns for remote memory access in an unloaded network, which is an order of magnitude lower than state-of-the-art Ethernet-based solutions such as RoCEv2 and comparable to emerging PCIe-based solutions such as CXL. Larger-scale network simulations indicate that even at high network loads, EDM's average latency remains within 1.3$\times$ its unloaded latency.

Figures

Figures reproduced from arXiv: 2411.08300 by the authors.

Figure 1
Figure 1. Memory disaggregation over Ethernet. PCIe, which dramatically reduce the interconnect latency to the NIC [73, 75, 78, 79, 86]. The demand for lower la￾tency for cloud services has also prompted tighter integration of the processor and memory with the network controller, which promises to reduce the processor/memory to NIC la￾tency to sub-100 ns. Such designs exist both in academia (e.g., nanoPU [30], soNUMA [49], FA… view at source ↗
Figure 2
Figure 2. Data path for memory traffic in EDM vs. in existing Ethernet fabrics for memory disaggregation. • Limitation 6: Queuing delay and drops at the switch. Most datacenter congestion control protocols are reactive in nature [1–3, 31, 42], i.e., they rely on some form of congestion feedback to handle congestion. Thus they can￾not eliminate queuing, especially for many-to-one (incast) traffic pattern. Memory traffic is ext… view at source ↗
Figure 3
Figure 3. EDM network stack. frame starts with an /S/ control block, followed by several /D/ data blocks, and ends with a /T/ control block. Ethernet also has a special /E/ control block that is typically used to make up the IFG. Each control block has a sync header value of "01" and an 8-bit block type, followed by 56 bits of payload (which could be frame data). The data block has sync header value of "10" and 64 bits of pay… view at source ↗
Figures from the paper (4 more)
Figure 4
Figure 4. Figure 4: Testbed setup. 4 Evaluation We evaluated the performance of EDM using an FPGA-based hardware testbed and large-scale network simulations. 4.1 Hardware Prototype We implemented EDM’s traffic scheduler (§3.1) and the host and switch stacks (§3.2) in Verilog by modifying …
Figure 5
Figure 5. Figure 5: Breakdown of latency for EDM’s network fabric for 64 B read and write. TD+PD = transmission+propagation delay. A clock cycle is 2.56 ns. For details on the cycle num￾bers refer to §3.2.1 and §3.2.2. scheduler ensures no congestion and packet drops, thus ob￾viating the …
Figure 7
Figure 7. Figure 7: End-to-end latency for YCSB workload. 4.2.2 Real application performance. We implemented a remote key-value store on EDM’s testbed and used a cycle￾accurate FPGA hardware simulator to evaluate EDM against the baselines using the YCSB workload [18]. Bandwidth utilizatio…
Figure 8
Figure 8. Figure 8: Network simulation. would consequently block or slow down all other ingress ports that have traffic destined to the victim. This is similar to head-of-line blocking in PFC [95]. In addition, we also conducted an experiment that in￾cluded a mixture of RREQ and WREQ in d…

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Pith tools

Reviewed August 12, 2026 · model on record in the stance chip above.