Exploring the Sparsity-Quantization Interplay on a Novel Hybrid SNN Event-Driven Architecture

Ilkin Aliyev; Jesus Lopez; Tosiron Adegbija

REVIEW 3 major objections 3 minor 15 references

Exploring the Sparsity-Quantization Interplay on a Novel Hybrid SNN Event-Driven Architecture

T0 review · 3 major / 3 minor · reviewed 2026-08-12 · deepseek-v4-flash

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Pith's one-line read A hybrid FPGA with a dense core for the first layer and sparse event-driven cores for the rest makes direct-coded spiking neural networks more accurate and 26.4x more energy-efficient than rate coding, while 4-bit quantization itself…

desk verdict Solid FPGA architecture paper with a real sparsity-quantization finding, but the headline direct-vs-rate claim conflates coding scheme with timestep count and needs matched baselines. read the letter →

arxiv 2411.15409 v1 pith:VLWRXL5P submitted 2024-11-23 cs.AR

Ilkin Aliyev , Jesus Lopez , Tosiron Adegbija This is my paper · ORCID

classification cs.AR

keywords spikingneuralnetworksdirectcodingrateFPGAacceleratorquantizationsparsityevent-drivenarchitecturehybrid

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper tries to establish that direct coding, not rate coding, is the right way to feed spiking neural networks when the accelerator is shaped to the network's layer mix. It reports a hybrid FPGA design with a dense core for the raw-input first layer and sparse event-driven cores for the rest, and it quantifies how 4-bit quantization changes spiking behavior. On CIFAR10, direct coding at 2 timesteps reaches 87.01% accuracy versus 77.37% for rate coding at 25 timesteps, with 2.6x fewer spikes and 26.4x less energy per image. Quantization increases sparsity by up to 15.2% across three datasets with accuracy losses below 3.1%, and the int4 design consumes 3.4x less energy than the fp32 design. If these results hold, direct coding plus quantization becomes the more attractive path for energy-efficient SNN inference, contrary to the earlier claim that rate coding is more energy efficient.

What carries the argument

The load-bearing mechanism is the hybrid core layout: a dense, weight-stationary systolic core for the first convolution layer, whose activations are non-binary and non-sparse, plus sparse event-driven cores for the remaining layers, where a compression routine uses a priority encoder to extract spike addresses and neural cores accumulate membrane potentials. A layer-wise workload model allocates core sizes, clock gating deactivates unused memory regions, and quantization-aware training produces the 4-bit integer weights; the leaky integrate-and-fire neuron (membrane potential update $u_j[t+1] = \beta u_j[t] + \sum_i w_{ij} s_i[t] - s_j[t]\theta$, spike if $u_j[t] > \theta$) drives all spiking.

What would settle it

Run the same direct-coded and rate-coded networks on the same hybrid hardware at equal timestep counts (or at timesteps chosen to equalize accuracy), and measure energy per image; if the 26.4x ratio shrinks to a small factor or inverts, the central coding-scheme advantage is not supported.

Watch

Extended reading notes

Core claim

The paper's central claim is that direct-coded SNNs are not inherently less efficient than rate-coded ones; they just need hardware that matches their structure. On the proposed hybrid architecture, the direct-coded VGG9 on CIFAR10 uses only 2 timesteps, emits 41K spikes versus 107K for rate coding at 25 timesteps, reaches 87.01% accuracy versus 77.37%, and consumes 7.6 mJ per image versus 201 mJ, a 26.4x improvement. The authors also claim that quantizing weights and biases to 4-bit integers increases sparsity by 6.1-15.2% across SVHN, CIFAR10, and CIFAR100, and that this sparsity gain, on top of the arithmetic power savings, yields a 3.4x energy reduction compared to the full-precision design.

Load-bearing premise

The strongest energy claim rests on comparing direct coding at 2 timesteps against rate coding at 25 timesteps, so the 26.4x energy gap could come mostly from the smaller number of timesteps rather than from direct coding itself; the paper does not report a matched-timestep or matched-accuracy control.

Editorial extensions

If this is right

Direct coding can be the preferred encoding for SNN inference when the accelerator has a dense core for the input layer and sparse cores for the rest, reducing both latency and energy.
Quantization can be treated as a sparsity-inducing regularizer during training, not just a compression step, yielding fewer spikes and 3.4x lower energy with minimal accuracy loss.
Layer-wise workload models that allocate core sizes from measured spike counts make heterogeneous FPGA designs practical for a given network.
The on-chip-only memory strategy limits the design to networks that fit in FPGA BRAM and URAM; scaling to larger models will require off-chip memory and will change the energy picture.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

The 26.4x energy ratio probably overstates direct coding's intrinsic advantage, because the comparison confounds timestep count, spike count, accuracy, and hardware configuration; a controlled study at equal accuracy would give a fairer number.
Quantization-induced sparsity may be a side effect of quantization noise acting as a regularizer during training; deliberately injecting noise without quantizing weights could test whether the sparsity effect is due to noise or to the integer constraint itself.
The hybrid dense-plus-sparse principle should transfer beyond image classifiers to any SNN with a dense first stage and sparse later stages, such as audio or video encoders; measuring on those inputs would test the architecture's generality.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Worth a serious look: the hybrid dense/sparse accelerator for direct-coded SNNs is a real engineering contribution, code is available, and the empirical observation that int4 QAT increases sparsity by 6.1-15.2% across three datasets is new and clean. The architecture description is careful, with sensible choices like a dense core for the non-sparse input layer, sparse event-driven cores for the rest, clock gating, and on-chip memory only. The synthesis results are reported per instance, which helps. The soft spot is the headline claim. Table II compares direct coding at 2 timesteps (87.01%, 7.6 mJ) with rate coding at 25 timesteps (77.37%, 201 mJ). Those runs differ in timestep count, spike count, accuracy, and hardware (dense core on/off). The 26.4x energy ratio mostly reflects running 12.5x fewer timesteps, not the coding scheme itself. The rate-coded accuracy looks low for VGG9 on CIFAR10; a properly tuned rate baseline might close the accuracy gap and reduce the energy gap substantially. The unsupported statement that further increasing the timesteps plateaued the accuracy does not fix this. The paper needs a matched-timestep or matched-accuracy control before claiming direct coding is inherently better. The same issue hits Table III: the 51x throughput versus [7] compares VGG9 to VGG11 with 3.1% lower accuracy, so that is not apples-to-apples. Power and energy are synthesis estimates, not board measurements, and there are no error bars on any accuracy or spike-count numbers. To be clear, the sparsity-quantization result stands on its own and does not depend on the problematic comparisons. The workload model being calibrated with the same hardware's measured spike counts is a design choice, not circular. The architecture is plausible, and the paper is honest about limitations like fp32 memory pressure and on-chip constraints. Send it to peer review but require the authors to rerun direct-vs-rate at matched timesteps or matched accuracy, report measured power or clearly label estimates, and include variance across seeds. The neuromorphic hardware audience will get value from the architecture and the sparsity-quantization data, but the central energy claim needs to be reworked.

Referee Report

3 major / 3 minor

Summary. The paper proposes a hybrid FPGA accelerator for direct-coded spiking neural networks, using a dense core for the first layer and sparse event-driven cores for subsequent layers. It reports three main results: (i) 4-bit quantization increases network sparsity by 6.1-15.2% on SVHN/CIFAR10/CIFAR100 with small accuracy loss, yielding up to 3.4x energy savings; (ii) direct coding at 2 timesteps outperforms rate coding at 25 timesteps on CIFAR10, with 10% higher accuracy and 26.4x lower energy; and (iii) the proposed accelerator achieves 51x higher throughput and half the power of prior work [7]. The paper includes open-source training and hardware code.

Significance. The hybrid dense/sparse architecture and the sparsity-quantization measurement are useful contributions: the layer-wise resource partitioning is concrete, the synthesis results on a Virtex UltraScale+ are reported in detail, and the finding that quantization consistently reduces spike counts across three datasets is empirically well grounded. The reproducibility artifacts strengthen the paper. However, the headline claims about direct coding and the 51x throughput comparison are currently not established because the comparisons conflate coding scheme with timestep count, and the throughput comparison uses different networks. If the authors add matched-baseline experiments and correct the reported ratios, the paper would make a solid contribution.

major comments (3)

[Section V-D, Table II] The direct-vs-rate comparison does not isolate the coding scheme. Direct coding is evaluated at 2 timesteps (87.01% accuracy, 41K spikes, 7.6 mJ) while rate coding is evaluated at 25 timesteps (77.37%, 107K spikes, 201 mJ). Because energy scales with the number of timesteps and spikes, the 26.4x energy improvement and the 10% accuracy gap could largely be an artifact of comparing 2 timesteps against 25, rather than a property of direct coding itself. Please add matched baselines: e.g., rate coding at 2 and 10 timesteps, direct coding at 25 timesteps, and/or a rate-coded network tuned to reach roughly 87% accuracy, and report the resulting energy and accuracy. Without such controls, the claim that direct coding 'outperforms' rate coding on this hardware is not established.
[Section V-D] The statement 'Further increasing the timesteps plateaued the accuracy for both schemes' is not supported by any data in the paper. The reader cannot tell whether 77.37% for rate coding at 25 timesteps is close to the rate-coding ceiling or an arbitrarily weak operating point. Please include accuracy-versus-timestep curves for both coding schemes (and, if possible, spike-count and energy curves) so the chosen operating points can be judged.
[Section V-E, Table III] The 51x throughput claim is not consistent with the numbers in Table III: 218 FPS divided by 4.7 FPS is 46.4x, not 51x. More fundamentally, the comparison against [7] uses different networks (VGG9 with 56.9% accuracy versus VGG11 with 60.1% accuracy on CIFAR100), so the throughput and power differences confound architecture with model size and accuracy. Please compare on the same network, or at least report the ratio with an explicit caveat that the networks differ.

minor comments (3)

[Equation (3)] In Equation (3), S_i is described only as 'the number of spikes for input feature map i'; please define whether this is per timestep or summed over all timesteps, and give the units of W_CONV and W_FC.
[Section V-B, Table I] There is an inconsistency in the reported LUT utilization: the text says 'the fp32 and int4 designs occupy 24% and 34% of the FPGA's LUT resources,' but Table I reports int4 utilization of 6.43% and fp32 utilization of 47.73%. Please correct the text or the table and clarify which percentages are being reported.
[Section IV-B] The sentence 'The architecture unrolls the output channels by a factor of N, defined as a top-level parameter, to determine the number of NC instances' uses the same symbol N as the max-pooling downsampling ratio in the preceding paragraph; please use distinct symbols to avoid confusion.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity found: the paper's claims are empirical measurements against external baselines; the workload model is a design-calibration step, not a derived prediction.

full rationale

The paper's central claims are empirical rather than derived. The quantization-sparsity finding (Section III, Fig. 1) reports measured spike counts and accuracies for fp32 versus int4 VGG9 networks; sparsity is an observed outcome, not an input fitted to produce the claimed 6.1-15.2% reductions. The direct-versus-rate coding comparison (Section V-D, Table II) is a hardware measurement of spikes, latency, and energy; the comparison is confounded by differing timestep counts and accuracy targets, but a confounded comparison is a correctness/experimental-design concern, not circular reasoning, because no quantity is defined in terms of the claimed conclusion. Equation 3's workload model uses empirically acquired spike counts to guide layer-wise resource partitioning; this is a design-time calibration step, and the reported energy/latency/throughput results come from post-synthesis measurements on the FPGA, not from the workload model itself. The one self-citation ([14], used to motivate a population-coded output layer) is backed by in-paper tuning ('Through experimentation, we found that the following P values provided the best accuracy'), so it is not load-bearing. No uniqueness theorem is imported, no prediction reduces by construction to a fitted parameter, and no known result is merely renamed. The hardware is evaluated against external works ([7], [15]) with independent metrics. Hence no significant circularity.

Assumptions & free parameters 6 free parameters · 5 assumptions · 0 invented entities

The central claims rest on tuned SNN hyperparameters (beta, theta, population size), a chosen timestep comparison, and synthesis-based power estimates rather than measured silicon. No new physical entities are introduced.

free parameters (6)

LIF decay beta = 0.15
Tuned by the authors; directly controls membrane potential decay and affects spike counts and accuracy.
LIF threshold theta = 0.5
Tuned together with beta; controls firing rate and thus all sparsity and energy numbers.
Output population P = 1000 for CIFAR10/SVHN; 5000 for CIFAR100
Chosen through experimentation to maximize accuracy with minimal spike train length, affecting energy and accuracy comparisons.
Per-layer neural core allocation = e.g., (1,28,12,54,16,72,70,19,4) for CIFAR100 perf2
Chosen empirically to balance layer-wise latency; these allocations determine the reported throughput and power.
Timesteps for direct and rate coding = 2 and 25, respectively
This comparison setting drives the 26.4x energy claim; it is a free choice rather than a controlled variable.
Quantization bit width = 4-bit integer (int4)
Chosen as the quantized precision; the sparsity and energy results are specific to this width.

assumptions (5)

domain assumption LIF neuron dynamics (Equations 1 and 2) adequately model the spiking behavior used in training and hardware.
All sparsity, accuracy, and energy results assume this neuron model with fixed beta and theta.
domain assumption The input layer of a direct-coded SNN is dense and non-sparse, so a dedicated dense core is necessary.
Stated in Section IV: the input layer has non-binary, non-sparse activations. If input activations were sparse, the dense core would be underutilized.
domain assumption Synthesis-based dynamic power estimates approximate real device power.
Tables I and III and Figure 4 use Vivado power estimates, not measurements on the FPGA board, so reported power and energy rest on this tooling assumption.
domain assumption Spike counts from a single hardware run are representative for workload balancing.
Equation 3 is calibrated with spike counts acquired empirically by running the network once on the hardware, with no repeated-run variance reported.
ad hoc to paper Direct coding at fewer timesteps is the fair basis for comparing against rate coding.
The paper rejects fixed-timestep comparisons from prior work but provides no matched-timestep or matched-accuracy control, making this a paper-specific assumption.

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Cite this review

Pith. "Pith review of Exploring the Sparsity-Quantization Interplay on a Novel Hybrid SNN Event-Driven Architecture." pith.science (2026). https://pith.science/paper/VLWRXL5P

@misc{pith2026241115409,
  author       = {Pith},
  title        = {Pith review of: Exploring the Sparsity-Quantization Interplay on a Novel Hybrid SNN Event-Driven Architecture},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/VLWRXL5P}},
  note         = {Machine review of arXiv:2411.15409}
}

read the original abstract

Spiking Neural Networks (SNNs) offer potential advantages in energy efficiency but currently trail Artificial Neural Networks (ANNs) in versatility, largely due to challenges in efficient input encoding. Recent work shows that direct coding achieves superior accuracy with fewer timesteps than traditional rate coding. However, there is a lack of specialized hardware to fully exploit the potential of direct-coded SNNs, especially their mix of dense and sparse layers. This work proposes the first hybrid inference architecture for direct-coded SNNs. The proposed hardware architecture comprises a dense core to efficiently process the input layer and sparse cores optimized for event-driven spiking convolutions. Furthermore, for the first time, we investigate and quantify the quantization effect on sparsity. Our experiments on two variations of the VGG9 network and implemented on a Xilinx Virtex UltraScale+ FPGA (Field-Programmable Gate Array) reveal two novel findings. Firstly, quantization increases the network sparsity by up to 15.2% with minimal loss of accuracy. Combined with the inherent low power benefits, this leads to a 3.4x improvement in energy compared to the full-precision version. Secondly, direct coding outperforms rate coding, achieving a 10% improvement in accuracy and consuming 26.4x less energy per image. Overall, our accelerator achieves 51x higher throughput and consumes half the power compared to previous work. Our accelerator code is available at: https://github.com/githubofaliyev/SNN-DSE/tree/DATE25

Figures

Figures reproduced from arXiv: 2411.15409 by the authors.

**Figure 2.** Dense Core (DC) hardware architecture. Weight stationary dataflow - PEs in a row collectively work on one [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗

**Figure 3.** Sparse Core (SC) hardware architecture. With the (row, col) pairs provided, the Accum routine within each NC performs the accumulation phase of the LIF neuron. It reads the membrane potential value from the BRAM, updates them with corresponding coefficient weights, and writes back the result to the BRAM. Similar to the dense core, the sparse cores also support quantization. Also, note that both the Address Generatio… view at source ↗

Figures from the paper (1 more)

**Figure 4.** Figure 4: Energy comparison for fp32 vs int4 hardware. The LW configurations are (1, 7, 1, 8, 2, 4, 14, 1, 2), (1, 8, 4, 18, 6, 6, 20, 2, 1) and (1, 7, 3, 12, 4, 18, 16, 4, 1) for SVHN, CIFAR10 and CIFAR100 respectively snnTorch [12]. The network, trained using surrogate gradien…

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

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Pith tools

Reviewed August 12, 2026 · model on record in the stance chip above.

[1] [7]

A resource- efficient spiking neural network accelerator supporting emerging neural encoding,

D. Gerlinghoff, Z. Wang, X. Gu, R. S. M. Goh, and T. Luo, “A resource- efficient spiking neural network accelerator supporting emerging neural encoding,” in 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 92–95, IEEE, 2022

work page 2022

[2] [1]

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W. Guo, M. E. Fouda, A. M. Eltawil, and K. N. Salama, “Neural coding in spiking neural networks: A comparative study for robust neuromorphic systems,” Frontiers in Neuroscience, vol. 15, p. 638474, 2021

work page 2021

[3] [2]

Conversion of analog to spiking neural networks using sparse temporal coding,

B. Rueckauer and S.-C. Liu, “Conversion of analog to spiking neural networks using sparse temporal coding,” in 2018 IEEE international symposium on circuits and systems (ISCAS) , pp. 1–5, IEEE, 2018

work page 2018

[4] [3]

Direct training for spiking neural networks: Faster, larger, better,

Y . Wu, L. Deng, G. Li, J. Zhu, Y . Xie, and L. Shi, “Direct training for spiking neural networks: Faster, larger, better,” in Proceedings of the AAAI conference on artificial intelligence , vol. 33, pp. 1311–1318, 2019

work page 2019

[5] [4]

Rate coding or direct coding: Which one is better for accurate, robust, and energy-efficient spiking neural networks?,

Y . Kim, H. Park, A. Moitra, A. Bhattacharjee, Y . Venkatesha, and P. Panda, “Rate coding or direct coding: Which one is better for accurate, robust, and energy-efficient spiking neural networks?,” in ICASSP 2022- 2022 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), pp. 71–75, IEEE, 2022

work page 2022

[6] [5]

Efficient hardware acceleration of sparsely active convolutional spiking neural networks,

J. Sommer, M. A. ¨Ozkan, O. Keszocze, and J. Teich, “Efficient hardware acceleration of sparsely active convolutional spiking neural networks,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 11, pp. 3767–3778, 2022

work page 2022

[7] [6]

Deepfire2: A convolutional spiking neural network accelerator on fpgas,

M. T. L. Aung, D. Gerlinghoff, C. Qu, L. Yang, T. Huang, R. S. M. Goh, T. Luo, and W.-F. Wong, “Deepfire2: A convolutional spiking neural network accelerator on fpgas,” IEEE Transactions on Computers, vol. 72, no. 10, pp. 2847–2857, 2023

work page 2023

[8] [8]

The parameters of the stochastic leaky integrate-and-fire neuronal model,

P. Lansky, P. Sanda, and J. He, “The parameters of the stochastic leaky integrate-and-fire neuronal model,” Journal of Computational Neuroscience, vol. 21, pp. 211–223, 2006

work page 2006