A Prototype-Based Framework to Design Scalable Heterogeneous SoCs with Fine-Grained DFS

Andrea Galimberti; Davide Zoni; Gabriele Montanaro

REVIEW 2 major objections 4 minor 10 references

A Prototype-Based Framework to Design Scalable Heterogeneous SoCs with Fine-Grained DFS

T0 review · 2 major / 4 minor · reviewed 2026-08-12 · deepseek-v4-flash

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Pith's one-line read Multi-replica tiles push SoC accelerator throughput up to 3.58x.

desk verdict Vespa is a solid, openly released extension of ESP, but its Kx throughput claim only holds for compute-bound accelerators, and the data show a common shared-path ceiling for memory-bound ones. read the letter →

arxiv 2411.15574 v2 pith:U2D7DMTA submitted 2024-11-23 cs.AR

Gabriele Montanaro , Andrea Galimberti , Davide Zoni This is my paper · ORCID

classification cs.AR

keywords system-on-chipFPGAprototypingnetwork-on-chipdynamicfrequencyscalinghardwareacceleratorreplicationdesignspaceexplorationrun-timemonitoring

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Vespa is an open-source framework for building large FPGA-based heterogeneous systems-on-chip whose tiles can be reconfigured to trade throughput against area, run at per-island clock frequencies, and report their own performance statistics. Its central idea is the multi-replica accelerator tile: K copies of the same AXI-based accelerator occupy a single network-on-chip node behind one bridge, so the designer can raise accelerator throughput without touching the accelerator or the interconnect. The framework also partitions the SoC into frequency islands with independent dynamic-frequency-scaling actuators that keep the clock running during reconfiguration, and it provides memory-mapped counters for execution time, packet counts, and memory round-trip time. On a 4-by-4 tile prototype, 2x and 4x replication give average throughput increases of 1.92x and 3.58x, with DSP usage growing roughly linearly while the other resource classes grow more slowly. The paper argues these capabilities make FPGA prototypes usable for design space exploration and run-time optimization of complex accelerator-centric SoCs.

What carries the argument

The load-bearing object is the multi-replica accelerator (MRA) tile: K copies of one accelerator, each exposing AXI4-Stream interfaces for read control, write control, read data, and write data, multiplexed by a single AXI bridge into the tile's four buffers toward the NoC. The replication factor K is a design-time parameter, so scaling requires no change to the accelerator or the network. Two mechanisms support the rest of the framework: frequency islands whose clocks come from either a fixed source or a dynamic frequency scaling (DFS) actuator built from two clock managers so one keeps the island clock alive while the other reconfigures, and memory-mapped counters that record accelerator execution time, incoming and outgoing packets, and round-trip time.

What would settle it

Measure the throughput of a memory-bound accelerator placed in a 4x-replication tile while NoC traffic is varied. If the K=4 tile does not deliver roughly four times the K=1 tile's throughput under light traffic, or if its throughput saturates at a value that does not change with K, the Kx scaling claim is falsified.

Watch

Extended reading notes

Core claim

The paper's central claim is that an accelerator's throughput can be scaled by an integer factor K simply by instantiating K replicas of it in one tile, and that this configurable replication, combined with per-island dynamic frequency scaling and run-time counters, is enough to support design space exploration and run-time optimization of a large SoC. The evidence is that 2x and 4x replication raise average throughput by 1.92x and 3.58x on the evaluated accelerators, while the same experiments show that a memory-bound accelerator loses throughput as NoC traffic rises, so the near-Kx scaling holds when the accelerator, not the bridge, NoC, or memory, is the limiting resource.

Load-bearing premise

The K-times throughput gain assumes the accelerator is the bottleneck; it breaks when the AXI bridge, the network-on-chip, or memory saturates first.

Editorial extensions

If this is right

A designer can tune each accelerator's throughput-versus-area trade-off with a single parameter, without editing accelerator RTL or resizing the NoC.
Software or host logic can change the clock of each island separately at run time, so the SoC frequency can adapt to the workload without stopping the island's clock.
The memory-mapped counters give a uniform way to watch accelerator execution, packet traffic, and memory round-trip latency during both exploration and deployed operation.
Because DSP blocks scale roughly with K while other resources scale less, replication is most area-efficient for accelerators whose replication cost is dominated by non-DSP logic.
The reported 1.92x and 3.58x average gains indicate that first-order throughput scaling by replication is achievable on FPGA prototypes for accelerators that are not memory-bound.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

A natural extension the paper does not develop is to use the counters to close a feedback loop: a run-time policy could raise an island's frequency when its accelerator is the bottleneck and lower it when memory traffic saturates.
The saturation of dfadd and dfmul near 26 MB/s at 4x replication suggests the AXI bridge or memory path becomes the next bottleneck; testing higher values of K would reveal the ceiling of this approach.
The same MRA tile could be paired with multiple bridge paths or wider NoC links to push the scaling limit, an option the paper leaves on the table.
A designer could use the framework to build a Pareto-optimal set of SoC configurations in replication, frequency, and placement before committing to a final design.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

The paper is worth reading if you work with ESP or FPGA prototyping of heterogeneous SoCs. The new and real thing is the Vespa framework: multi-replica accelerator tiles that keep the same AXI interface to the NoC, glitch-free dual-MMCM DFS actuators per frequency island, and memory-mapped monitoring counters. It is open source, the experimental setup is described in enough detail to reproduce, and the resource/throughput tables are concrete. This is a genuine engineering contribution, not a reparameterization of prior work.

The soft spots are in the scaling claim. Section II-A says that K replicas 'intuitively provide a Kx increase of throughput.' The data in Table I show that dfadd and dfmul both hit exactly 26.06 MB/s at 4x replication despite very different 1x throughputs. That is a red flag for a shared bottleneck, likely the AXI bridge or the NoC/memory path. The stress-test note is right: the headline Kx scaling is only established for lightly loaded, compute-bound accelerators. The paper does call dfadd memory-bound and Fig. 3 shows dfmul collapsing under NoC traffic, so the authors are not hiding the data, but the claim in the introduction and conclusion is overbroad. That is a moderate flaw, not a fatal one.

Two other minor issues: there are no error bars or multiple runs, which is common for FPGA prototype papers but worth noting; and there is no baseline against plain ESP to show what Vespa adds in area or performance. These are minor because the framework ships and the qualitative behavior is clear.

The circularity burden is truly low: no fitted parameters, no self-defined success metric, just direct measurements of real hardware. Self-citations are used to motivate the work, not to carry the central result.

Who gets value: researchers doing DSE on FPGA-based SoCs, especially those using ESP who want accelerator replication, DFS islands, and monitoring without writing RTL from scratch. It is a niche but active audience.

Recommendation: send it to peer review. It deserves referee time. I would ask the authors to qualify the Kx claim to compute-bound accelerators and add a sentence acknowledging the shared-path ceiling, but I would not reject it over that.

Referee Report

2 major / 4 minor

Summary. The paper presents Vespa, an open-source framework that extends ESP to support design space exploration and runtime optimization of FPGA-based multi-core heterogeneous SoCs. Three main capabilities are added: multi-replica accelerator tiles that instantiate K copies of an AXI-compatible accelerator within a single NoC node, configurable frequency islands with independent DFS actuators (using a dual-MMCM scheme to avoid clock-gating during reconfiguration), and a memory-mapped monitoring infrastructure that exposes execution time, packet counts, and round-trip time. The evaluation on a 4x4 tile-based SoC implemented on a Virtex-7 2000 FPGA shows resource and throughput trade-offs for 2x and 4x replication of five CHStone accelerators, the throughput behavior of compute- versus memory-bound accelerators under NoC traffic, and the effect of island clock frequencies on memory traffic.

Significance. If the claims hold, Vespa is a valuable open-source contribution: it provides a practical way to explore accelerator replication and fine-grained frequency-island partitioning on real FPGA prototypes, and the dual-MMCM DFS mechanism addresses a genuine problem in FPGA clock reconfiguration. The monitoring infrastructure is a useful enabler for run-time optimization. The paper ships open source, and the experiments are direct measurements on implemented hardware with no fitted parameters. However, the central throughput-scaling claim is only partially supported by the data, and the reported quantitative results contain an inconsistency that needs correction.

major comments (2)

[§II-A, §III-A, Table I] The claim that instantiating K replicas "intuitively provides a K× increase of the throughput of the baseline accelerator" is not supported for memory-bound accelerators. In Table I, dfadd and dfmul both saturate at exactly 26.06 MB/s at 4x replication despite having different baseline throughputs (9.22 and 8.70 MB/s), which indicates a shared resource limit—likely the AXI bridge, the NoC link, or the memory controller—rather than the accelerator itself. Section III-B further shows that dfmul throughput collapses as NoC traffic increases. The paper should qualify the Kx scaling claim to compute-bound accelerators and state the conditions under which the bridge/NoC/memory path is not the bottleneck; this is load-bearing because the conclusion describes Vespa as a "scalable throughput architecture."
[§III-A, Table I] The reported average throughput increases of 1.92x and 3.58x for 2x and 4x replication do not match the data in Table I. Computing the average of the per-accelerator throughput ratios from the table gives 1.89x and 3.41x, and the latter value actually appears in the "Incr." row of Table I. The 3.58x figure appears to be an arithmetic error or to be based on a different set of accelerators. Please correct the numbers and, more importantly, report per-accelerator throughput ratios so that the saturation of dfadd and dfmul is transparent.

minor comments (4)

[§III-A] Please clarify whether each throughput value in Table I is the result of a single execution or the average of multiple runs; if multiple runs were performed, include error bars or variance, especially for the key replication measurements.
[§III] The core name "CV A6" should be written "CVA6" (or "Ariane") as in reference [9].
[§III-A] The phrase "quite smaller than the replication factor" is awkward; consider "substantially smaller" or "significantly smaller."
[Fig. 1] The figure legend uses "Resync" and "resychronizers" (typo); it should be "resynchronizers" consistently. The labels "DFSm" and "DFSn" are also visually confusing and could be clarified.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: all reported results are direct measurements of implemented FPGA prototypes; self-citations are motivational and not load-bearing.

full rationale

The paper's central claims—that Vespa supports configurable multi-replica accelerator tiles, independent DFS frequency islands, and memory-mapped run-time monitoring—are architectural contributions validated by post-implementation resource numbers and run-time throughput and traffic measurements (Table I, Figs. 2-4). No parameter is fitted to a subset of data and then renamed as a prediction; the reported 1.92x and 3.58x average throughput increases are arithmetic summaries of the measured throughput columns in Table I, not derived predictions. The Kx statement in Section II-A is a stated design rationale for the architecture, and the measured data are reported openly, including cases where memory-bound accelerators saturate at the same ceiling; this is a correctness or bottleneck qualification of the Kx claim, not a circular reduction. Self-citations [1], [3], and [7] motivate the application domain and the need for run-time monitoring, but none of them supplies the load-bearing derivation of the framework's functionality or evaluation. The experiments are direct observations of the implemented hardware, so no significant circularity is present.

Assumptions & free parameters 2 free parameters · 4 assumptions · 0 invented entities

The central claims rest on standard hardware and vendor assumptions rather than fitted parameters. The only hand-chosen variables are experimental knobs (replication factor, clock ranges), and no invented physical entities are introduced.

free parameters (2)

Replication factor K = 1, 2, 4
Design-time knob for number of accelerator replicas per tile. Not fitted, but the scaling claim is evaluated only at these hand-chosen values.
Frequency island clock ranges = 10-100 MHz for NoC/MEM; 10-50 MHz for other islands at 5 MHz steps
Hand-chosen experimental settings that define the DFS demonstration; results may not generalize to other ranges.

assumptions (4)

domain assumption Third-party accelerators expose four AXI4-Stream interfaces
The multi-replica tile design and AXI bridge multiplexing are built on this interface contract (Section II-A).
domain assumption AMD MMCM output clock stays low during reconfiguration
Motivates the dual-MMCM DFS actuator to avoid clock gating (Section II-B).
domain assumption CHStone HLS benchmarks are representative of accelerator-centric workloads
All five accelerators come from CHStone and are used to draw general throughput and scalability conclusions (Section III).
domain assumption ESP is a valid baseline tile-based SoC architecture
Vespa is built on ESP and inherits its NoC, tile, and integration assumptions (Sections I-II).

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Cite this review

Pith. "Pith review of A Prototype-Based Framework to Design Scalable Heterogeneous SoCs with Fine-Grained DFS." pith.science (2026). https://pith.science/paper/U2D7DMTA

@misc{pith2026241115574,
  author       = {Pith},
  title        = {Pith review of: A Prototype-Based Framework to Design Scalable Heterogeneous SoCs with Fine-Grained DFS},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/U2D7DMTA}},
  note         = {Machine review of arXiv:2411.15574}
}

read the original abstract

Frameworks for the agile development of modern system-on-chips are crucial to dealing with the complexity of designing such architectures. The open-source Vespa framework for designing large, FPGA-based, multi-core heterogeneous system-on-chips enables a faster and more flexible design space exploration of such architectures and their run-time optimization. Vespa, built on ESP, introduces the capabilities to instantiate multiple replicas of the same accelerator in a single network-on-chip node and to partition the system-on-chips into frequency islands with independent dynamic frequency scaling actuators, as well as a dedicated run-time monitoring infrastructure. Experiments on 4-by-4 tile-based system-on-chips demonstrate the possibility of effectively exploring a multitude of solutions that differ in the replication of accelerators, the clock frequencies of the frequency islands, and the tiles' placement, as well as monitoring a variety of statistics related to the traffic on the interconnect and the accelerators' performance at run time.

Figures

Figures reproduced from arXiv: 2411.15574 by the authors.

**Figure 1.** Architecture of a generic Vespa SoC with multi-replica accelerator tiles and configurable-DFS frequency islands. Example [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗

**Figure 2.** Floorplan of an instance of the Vespa SoC architecture. [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗

**Figure 3.** Throughput of 4×-replication compute-bound (adpcm) and memory-bound (dfmul) accelerators placed in the A2 tile at different numbers of active TG cores. depicts the throughput of the adpcm and dfmul accelerators with a number of active TG cores ranging between 0, i.e., when all of them are disabled, and 11, i.e., when all the TG cores in the SoC are enabled. The NoC interconnect runs at 10MHz while the accelerators a… view at source ↗

Figures from the paper (1 more)

**Figure 4.** Figure 4: Memory incoming traffic while varying at run time the [PITH_FULL_IMAGE:figures/full_fig_p004_4.png]

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

10 extracted references · 8 canonical work pages

[1]

Galimberti, D

A. Galimberti, D. Galli, G. Montanaro, W. Fornaciari, and D. Zoni, ``Fpga implementation of bike for quantum-resistant tls,'' in 2022 25th Euromicro Conference on Digital System Design (DSD), 2022, pp. 539--547

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Y.-H. Chen, T. Krishna, J. S. Emer, and V. Sze, ``Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks,'' IEEE Journal of Solid-State Circuits, vol. 52, no. 1, pp. 127--138, 2017

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Galimberti, G

A. Galimberti, G. Montanaro, and D. Zoni, ``Hls-based acceleration of the bike post-quantum kem on embedded-class heterogeneous socs,'' in 2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2023, pp. 1--4

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Mantovani, D

P. Mantovani, D. Giri, G. Di Guglielmo, L. Piccolboni, J. Zuckerman, E. G. Cota, M. Petracca, C. Pilato, and L. P. Carloni, ``Agile soc development with open esp,'' in Proceedings of the 39th International Conference on Computer-Aided Design, 2020, pp. 1--9

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J. Balkind, T.-J. Chang, P. J. Jackson, G. Tziantzioulis, A. Li, F. Gao, A. Lavrov, G. Chirkov, J. Tu, M. Shahrad, and D. Wentzlaff, ``Openpiton at 5: A nexus for open and agile hardware design,'' IEEE Micro, vol. 40, no. 4, p. 22–31, jul 2020. [Online]. Available: https://doi.org/10.1109/MM.2020.2997706

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D. Zoni, A. Galimberti, and W. Fornaciari, ``A survey on run-time power monitors at the edge,'' ACM Comput. Surv., vol. 55, no. 14s, jul 2023. [Online]. Available: https://doi.org/10.1145/3593044

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Y. Hara, H. Tomiyama, S. Honda, H. Takada, and K. Ishii, ``Chstone: A benchmark program suite for practical c-based high-level synthesis,'' in 2008 IEEE International Symposium on Circuits and Systems (ISCAS), 2008, pp. 1192--1195

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Zaruba and L

F. Zaruba and L. Benini , ``The cost of application-class processing: Energy and performance analysis of a linux-ready 1.7-ghz 64-bit risc-v core in 22-nm fdsoi technology,'' IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 11, pp. 2629--2640, Nov 2019

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[10]

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Pith tools

Reviewed August 12, 2026 · model on record in the stance chip above.

[1] [1]

Galimberti, D

A. Galimberti, D. Galli, G. Montanaro, W. Fornaciari, and D. Zoni, ``Fpga implementation of bike for quantum-resistant tls,'' in 2022 25th Euromicro Conference on Digital System Design (DSD), 2022, pp. 539--547

work page 2022

[2] [2]

Y.-H. Chen, T. Krishna, J. S. Emer, and V. Sze, ``Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks,'' IEEE Journal of Solid-State Circuits, vol. 52, no. 1, pp. 127--138, 2017

work page 2017

[3] [3]

Galimberti, G

A. Galimberti, G. Montanaro, and D. Zoni, ``Hls-based acceleration of the bike post-quantum kem on embedded-class heterogeneous socs,'' in 2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2023, pp. 1--4

work page 2023

[4] [4]

Mantovani, D

P. Mantovani, D. Giri, G. Di Guglielmo, L. Piccolboni, J. Zuckerman, E. G. Cota, M. Petracca, C. Pilato, and L. P. Carloni, ``Agile soc development with open esp,'' in Proceedings of the 39th International Conference on Computer-Aided Design, 2020, pp. 1--9

work page 2020

[5] [5]

A. Amid, D. Biancolin, A. Gonzalez, D. Grubb, S. Karandikar, H. Liew, A. Magyar, H. Mao, A. Ou, N. Pemberton et al., ``Chipyard: Integrated design, simulation, and implementation framework for custom socs,'' IEEE Micro, vol. 40, no. 4, pp. 10--21, 2020

work page 2020

[6] [6]

Balkind, T.-J

J. Balkind, T.-J. Chang, P. J. Jackson, G. Tziantzioulis, A. Li, F. Gao, A. Lavrov, G. Chirkov, J. Tu, M. Shahrad, and D. Wentzlaff, ``Openpiton at 5: A nexus for open and agile hardware design,'' IEEE Micro, vol. 40, no. 4, p. 22–31, jul 2020. [Online]. Available: https://doi.org/10.1109/MM.2020.2997706

work page arXiv 2020

[7] [7]

D. Zoni, A. Galimberti, and W. Fornaciari, ``A survey on run-time power monitors at the edge,'' ACM Comput. Surv., vol. 55, no. 14s, jul 2023. [Online]. Available: https://doi.org/10.1145/3593044

doi:10.1145/3593044 2023

[8] [8]

Y. Hara, H. Tomiyama, S. Honda, H. Takada, and K. Ishii, ``Chstone: A benchmark program suite for practical c-based high-level synthesis,'' in 2008 IEEE International Symposium on Circuits and Systems (ISCAS), 2008, pp. 1192--1195

work page 2008