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REVIEW 3 major objections 6 minor 51 references

SiGe BiCMOS Circuit Design using only PMOS and HBTs Approach for the Ocean Worlds Exploration

T0 review · 3 major / 6 minor · reviewed 2026-08-12 · deepseek-v4-flash

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Pith's one-line read This paper argues that omitting NMOS entirely and building circuits from PMOS transistors and SiGe heterojunction bipolar transistors can make electronics that survive the 93 K, 5 Mrad(Si) surface of Europa without warm boxes or heavy…

desk verdict A clear survey of why PMOS+SiGe HBTs are promising for extreme environments, but no circuit or data to back the title claim. read the letter →

arxiv 2411.16093 v1 pith:NUEN5R6N submitted 2024-11-25 physics.ins-det physics.app-ph

Md Omar Faruk , Steven Corum , Zakaraya Hamdan , Alex Seaver , Travis Graham , Benjamin J. Blalock This is my paper · ORCID
classification physics.ins-detphysics.app-ph
keywords SiGeBiCMOSPMOS-onlydesigncryogenicelectronicstotalionizingdoseEuropasurfaceheterojunctionbipolartransistorhotcarriereffectrad-hardcircuit
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Standard CMOS electronics are poorly suited to the surface of Europa and similar ocean worlds: at 93 K, NMOS transistors suffer hot-carrier degradation that shortens their lifetime by about two orders of magnitude relative to PMOS, and under multi-megarad total ionizing dose they develop leakage currents and become hard to turn off. This paper argues that a BiCMOS design approach that simply omits NMOS, building circuits from PMOS transistors and SiGe heterojunction bipolar transistors (HBTs) only, can combine the cold-tolerant and radiation-tolerant strengths of both device types. It proposes an SRAM bit cell with ECL peripherals as the test vehicle, and asserts that this PMOS+HBT approach gives designers a way to use the best characteristics of PMOS, polysilicon resistors, and SiGe HBTs in extreme cold and radiation. The payoff, if the approach works, is electronics that operate directly on the icy surface without a warm electronics box or heavy shielding.

What carries the argument

The load-bearing object is the PMOS+HBT design approach: a circuit architecture that uses PMOS transistors (with their long cryogenic hot-carrier lifetime and TID-induced off-state) for logic and switching, SiGe heterojunction bipolar transistors (bipolar transistors with a graded germanium base, whose fT and fmax rise as temperature falls) for high-speed, analog, and emitter-coupled-logic functions, and polysilicon resistors as passive loads, with NMOS deliberately absent. The underlying mechanisms are the hot-carrier lifetime model τ Ids/W ∝ 1/(Isub/Ids)^α, which puts PMOS two orders of magnitude ahead of NMOS at 77 K, and the positive charge buildup in gate oxides under TID, which turns PMOS further off (no leakage) while making NMOS leaky. For the HBT side, the mechanism is the graded germanium base's quasi-drift field that accelerates electrons, together with the physical isolation of the damage-prone oxide interfaces from the carrier transport path, giving built-in TID tolerance.

What would settle it

Irradiate a PMOS+HBT SRAM test chip, fabricated on the target BiCMOS process, to 5 Mrad(Si) while operating it at 93 K, and monitor static noise margin, access time, and standby current over an accelerated lifetime; the claim is falsified if the circuit fails before the projected 20-30 year equivalent, or if PMOS-only logic shows hot-carrier degradation comparable to NMOS when the radiation and cryogenic stresses act together.

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Extended reading notes

Core claim

The paper's central claim is that the reliability liabilities of conventional BiCMOS at cryogenic temperature and high total ionizing dose come almost entirely from the NMOS transistor, and that a circuit design approach which excludes NMOS entirely, using only PMOS for the MOSFET functions and SiGe HBTs for high-speed and analog functions, can deliver environmentally invariant electronics for Europa-class missions. The authors review device-level evidence that PMOS has roughly two orders of magnitude longer hot-carrier lifetime than NMOS at 77 K, that PMOS leakage stays near zero under TID because trapped positive charge biases it further off, and that SiGe HBTs tolerate multi-megarad doses and actually improve in speed and gain when cooled to 4.5 K. From this, the paper concludes that a PMOS+HBT design approach gives circuit designers the chance to exploit the best characteristics of PMOS, polysilicon resistors, and SiGe HBTs in extreme cold and radiation, and it outlines a planned SRAM bit cell with ECL peripherals as the demonstration circuit. The paper does not claim to have built or measured this circuit; it is a design rationale and proposal.

Load-bearing premise

The whole approach rests on the assumption that the device-level reliability advantages measured separately for PMOS at 77 K and for SiGe HBTs under radiation will hold when combined in a complete circuit operating at 93 K and 5 Mrad(Si), with no new failure mode appearing in the interconnection of PMOS, polysilicon resistors, and ECL peripherals.

Editorial extensions

If this is right

  • A PMOS+HBT SRAM with ECL peripherals would be the first circuit demonstration of the approach; if it meets spec at 93 K and 5 Mrad(Si), it validates the design route without requiring specialized rad-hard process modifications.
  • Surface electronics for Europa landers could be placed directly at the point of use, at sensors, actuators, and drill motors, instead of being concentrated in a shielded warm box, enabling distributed, modular spacecraft architectures.
  • Because SiGe HBT fT and fmax rise as temperature falls (to roughly 450 GHz at 77 K in the cited data), the ECL peripherals would run faster in the mission environment than at room temperature, offsetting any speed penalty from PMOS-only logic.
  • The approach uses existing commercial BiCMOS processes, avoiding the annular-gate NMOS structures that most foundries do not support, so fabrication cost and availability would match standard commercial practice.
  • If the reliability equations quoted from 180 nm CMOS transfer to the chosen BiCMOS node, the projected circuit lifetime at cryogenic temperature could reach the 20-30 year target for Ocean Worlds missions.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The paper leaves circuit-level verification to future work; a direct extension is to characterize a PMOS-only inverter chain and ring oscillator at 93 K and after 5 Mrad(Si), separating logic-family viability from SRAM-specific issues like noise margin and writeability.
  • The proposal assumes radiation and cryogenic temperature act independently, since the cited device data treat them separately; a combined stress test (TID applied at 93 K) on the actual process would be a stronger validation and could reveal interactions such as radiation-enhanced hot-carrier trapping.
  • The same exclusion strategy could be evaluated for other extreme environments, such as lunar night at 43 K, high-luminosity particle detectors, or very hot operation, wherever NMOS is the limiting device and a complementary bipolar option exists.
  • The paper does not quantify power and speed tradeoffs of PMOS-only logic versus conventional CMOS at 93 K; a system-level comparison of ECL-peripheral power against a rad-hard CMOS implementation would clarify whether the reliability gain comes at an acceptable power cost.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 6 minor

Summary. The paper proposes a circuit design approach for extreme-environment (cryogenic and high-radiation) electronics targeting Ocean Worlds missions, using only PMOS transistors and SiGe HBTs in a BiCMOS platform. It reviews hot-carrier degradation in CMOS at cryogenic temperatures, the TID response of MOSFETs and SiGe HBTs, and the cryogenic/RF performance of SiGe HBTs, and concludes that the PMOS+HBT approach offers designers a route to robust electronics for Europa-class missions. The manuscript is explicitly framed as a dissertation proposal and contains no new derivations, no circuit-level schematics, no simulations, and no measurements.

Significance. If validated, the proposed approach would be significant for extreme-environment electronics, potentially enabling unshielded or minimally shielded electronics on Ocean Worlds surface missions. The paper correctly summarizes device-level reliability evidence from the literature, particularly the hot-carrier lifetime advantage of PMOS over NMOS at cryogenic temperatures and the multi-Mrad TID tolerance of SiGe HBTs. Its contribution is a well-referenced synthesis of known device data into a design strategy; however, the central feasibility claim is asserted rather than demonstrated, and the paper does not provide any quantitative circuit-level evidence that a complete PMOS+HBT SRAM with ECL peripherals would meet its functional requirements at 93 K and 5 Mrad(Si). The paper's strength lies in its accurate reporting of the cited device behavior, but that evidence alone does not establish the proposed design approach as a working solution.

major comments (3)
  1. [Sections IV-C and V] The central claim—that the PMOS+HBT approach 'gives circuit designers a chance' to utilize the best characteristics of PMOS, polysilicon resistors, and SiGe HBTs in extreme environments—is unsupported by any circuit-level demonstration. The manuscript presents no transistor-level schematic, no SPICE or system-level simulation, no static noise margin or write/read margin analysis, and no measured or post-layout results for an SRAM bit cell with ECL peripherals at the stated 93 K and 5 Mrad(Si) conditions. The cited device-level data (e.g., Refs. [19], [20], [26], [27]) come from separate technologies and stress conditions, and the paper does not show that the combined reliability advantages transfer to a complete circuit. This is the load-bearing gap: either add a concrete design study (even a simulation-based one) or explicitly limit the conclusion to a proposal rather than a demonstrated outcome.
  2. [Section II-A, Eqs. (3)-(5) and following text] The definition of the exponent α is misstated. The text after Eq. (5) reads 'α = ϕit/ϕi is the ratio of the critical energy of the electron to produce an interface state, ϕit (≈ 3.7-4.1eV), and the critical energy to generate an electron-hole pair through impact ionization, ϕit (≈ 1.3 eV)'—the second energy is ϕi, not ϕit. This symbol error makes the derivation of Eq. (5) from Eq. (4) appear circular, even though the lucky-electron model (e.g., Ref. [25]) gives τ·Ids/W ∝ (Isub/Ids)^(-ϕit/ϕi). Please correct the symbol and also fix the typo '2.9 m 3.2' to '2.9 to 3.2'.
  3. [Section II-A, paragraph on lifetime projection] The projected '2 orders of magnitude' lifetime advantage of PMOS over NMOS is based on 180-nm CMOS hot-carrier tests at 77 K (Refs. [17], [19]). The proposed circuit, however, would be implemented in a modern SiGe BiCMOS process (e.g., 90-nm or 130-nm). The manuscript does not explain how the hot-carrier lifetime and TID response of PMOS in that specific process compare, nor does it address the impact of PMOS becoming 'harder to turn on' under TID on SRAM write/read/hold margins. This is a quantitative gap that the authors need to fill to support the central claim.
minor comments (6)
  1. [Index Terms] The index term 'BiCOMS' should be 'BiCMOS'.
  2. [Section II-A] The notation 'm 2%' and 'm 10%' should be written as '≈ 2%' and '≈ 10%' to indicate approximate values.
  3. [Section I] The phrase 'The tell of life' in the first sentence of the Introduction should likely be 'The tale of life' or 'The story of life'.
  4. [References] Reference [12] is listed as 2022, but the IEEE Transactions on Nuclear Science volume and issue correspond to 2012; please verify and correct the year.
  5. [Section II-B, Eq. (6)] The term 'WCB/2vsat' is ambiguous; write it as WCB/(2·vsat) and define WCB as the collector-base depletion width for clarity.
  6. [Section II-A] In the sentence defining α, the second occurrence of 'ϕit' should be 'ϕi' (this is the same typo noted in the major comment, listed here for completeness).

Circularity Check

0 steps flagged · score 0.0 of 10

No circular derivation: all device equations and reliability data are imported from prior published experiments, and the proposal makes no fitted prediction that reduces to its own input.

full rationale

This paper is a dissertation proposal and does not advance an independent derivation chain. The MOSFET lifetime equations (1)-(5) are explicitly taken from Shaorui Li's and Jie Ma's published 180-nm CMOS measurements, and the SiGe HBT tolerance claims are quoted from Cressler and other experimental studies. No parameter in this paper is fitted to data and then renamed as a prediction, and no quantity is derived from a definition that already contains the target result. The self-citations that appear, such as references [13], [14], and [27] involving co-authors, point to external measured device data and prior design work, not to this paper's conclusion, so they do not form a load-bearing circular chain. The main weakness is an evidential gap rather than circularity: the paper motivates a PMOS+HBT SRAM/ECL approach using device-level measurements but does not present a complete circuit, schematic, or simulation, so the feasibility claim is asserted rather than demonstrated. The text also confuses the impact-ionization energy with the interface-trap creation energy in the vicinity of Eq. (5), but that is a correctness or typographical issue, not a circularity. Because no step reduces to its own input by construction, the circularity score is 0.

Assumptions & free parameters 0 free parameters · 5 assumptions · 0 invented entities

The paper introduces no fitted parameters, no new postulates, and no invented entities. All quantitative inputs are quoted from prior publications. The assumptions above are the domain-level premises on which the proposal rests, and each is an external literature claim rather than a derivation provided in this preprint.

assumptions (5)
  • domain assumption NMOS devices have a projected lifetime about two orders of magnitude shorter than PMOS at cryogenic temperatures due to hot carrier effects.
    This is the central motivation for excluding NMOS, quoted from Refs. [17] and [19], but not independently verified in this paper. It appears in Section II-A.
  • domain assumption Total ionizing dose radiation makes NMOS leaky and hard to turn off, while PMOS does not develop significant leakage.
    This underpins the PMOS-only choice in Section IV-A, based on Refs. [43] and [44], without any radiation test in the paper.
  • domain assumption SiGe HBTs maintain or improve their performance at cryogenic temperatures and tolerate multi-Mrad TID.
    The paper relies on this to put HBTs in the periphery; data are reproduced from Refs. [26], [30], and [52] in Sections II-B and III-B.
  • domain assumption The Europa surface environment has a temperature of 93 K and a total ionizing dose of 5 Mrad(Si), and COTS components cannot survive it.
    These mission parameters are taken from NASA documents cited in the introduction, not measured here.
  • domain assumption Commercial CMOS foundries do not offer annular-gate NMOS devices, so layout-based NMOS radiation hardening is unavailable.
    This argument appears in Section IV-A with citation [53], and it is used to justify removing NMOS entirely.

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Cite this review

Pith. "Pith review of SiGe BiCMOS Circuit Design using only PMOS and HBTs Approach for the Ocean Worlds Exploration." pith.science (2026). https://pith.science/paper/NUEN5R6N

@misc{pith2026241116093,
  author       = {Pith},
  title        = {Pith review of: SiGe BiCMOS Circuit Design using only PMOS and HBTs Approach for the Ocean Worlds Exploration},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/NUEN5R6N}},
  note         = {Machine review of arXiv:2411.16093}
}
read the original abstract

Space exploration to have the biosignatures of extraterrestrial life on different planets with oceans in our solar system and beyond requires the design and manufacturing of robust and reliable electronic systems that can be used for sensing, data processing, controlling motor/actuators, and communication while surviving an extreme environment. Commercial off the shelf (COTS) components cannot survive a long time in such harsh environments after being housed in a Warm Electronics Box, and any electronic system designed for such extreme conditions must be tailored to suit such operation. The presence of extremely cold temperatures and high radiation adversely affects the device parameters over time, i.e. the operation of electronic systems.

Figures

Figures reproduced from arXiv: 2411.16093 by the authors.

Figure 1
Figure 1. Europa’s interior Ocean (An artist’s view) [9]. [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. Schematic illustration of the stress of the Hot Carrier Effect (impact [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 3
Figure 3. Under accelerated stress, the transconductance degradation vs. time [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figures from the paper (11 more)
Figure 6
Figure 6. Figure 6: SiGe HBT cross-section. Where, EB-S = emitter-base spacer, FOX = [PITH_FULL_IMAGE:figures/full_fig_p004_6.png]
Figure 7
Figure 7. Figure 7: Schematic comparison in the energy band diagrams of a Si BJT and a [PITH_FULL_IMAGE:figures/full_fig_p005_7.png]
Figure 9
Figure 9. Figure 9: is the plot of the measured output characteristics of a commercial first-gen SiGe HBT at 27◦C (300 K) and −230◦C (43 K). The lowest temperature found on the Earth’s moon is −230◦C (43 K). Both pictures in [PITH_FULL_IMAGE:figures/full_fig_p006_9.png]
Figure 10
Figure 10. Figure 10: Radiation-induced charge generation processes are explained in the [PITH_FULL_IMAGE:figures/full_fig_p006_10.png]
Figure 11
Figure 11. Figure 11: Domination of the positively charged traps in most of the MOSFET [PITH_FULL_IMAGE:figures/full_fig_p006_11.png]
Figure 12
Figure 12. Figure 12: Possible leakage paths in a CMOS IC due to shallow trench isolation [PITH_FULL_IMAGE:figures/full_fig_p007_12.png]
Figure 13
Figure 13. Figure 13: The gate oxide transistor has increased leakage current because there [PITH_FULL_IMAGE:figures/full_fig_p007_13.png]
Figure 14
Figure 14. Figure 14: Pre and post-radiation I-V characteristics of a 3rd-gen SiGe HBT, [PITH_FULL_IMAGE:figures/full_fig_p008_14.png]
Figure 15
Figure 15. Figure 15: Pre and post-radiation cutoff frequency vs. bias current density for [PITH_FULL_IMAGE:figures/full_fig_p008_15.png]
Figure 16
Figure 16. Figure 16: The vulnerable points affiliated with the emitter-base (EB) spacer [PITH_FULL_IMAGE:figures/full_fig_p009_16.png]
Figure 17
Figure 17. Figure 17: Pre and post-radiation, I-V characteristics of a 1st-gen SiGe HBT at [PITH_FULL_IMAGE:figures/full_fig_p009_17.png]

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Pith tools

Reviewed August 12, 2026 · model on record in the stance chip above.