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REVIEW 3 major objections 6 minor 24 references

From CISC to RISC: language-model guided assembly transpilation

T0 review · 3 major / 6 minor · reviewed 2026-08-12 · deepseek-v4-flash

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Pith's one-line read This paper claims a 1.3B-parameter language model can transpile x86 assembly into executable ARM/RISC-V assembly with 79.25% and 88.68% functional accuracy, and that the transpiled ARM64 code beats Rosetta 2 on an M2 by 1.73x speed, 2.41x…

desk verdict A credible new empirical result in LLM-based assembly transpilation, with functional verification as the main strength; the headline accuracy needs a contamination audit and the case study needs more detail before the numbers are fully trusted. read the letter →

arxiv 2411.16341 v1 pith:G5C6XJRS submitted 2024-11-25 cs.PL cs.AR

Ahmed Heakl , Chaimaa Abi , Rania Hossam , Abdulrahman Mahmoud This is my paper · ORCID
classification cs.PLcs.AR
keywords assemblytranspilationCISCtoRISClanguagemodelx86ARMRISC-Vbinarytranslationfunctionalcorrectness
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper tries to establish that a small language model can act as a direct CISC-to-RISC assembly transpiler, converting x86 machine code into ARM and RISC-V assembly without the runtime overhead of an emulator or virtualization layer. Its central evidence is a fine-tuned 1.3B-parameter model that passes 79.25% of the HumanEval-derived test suite when translating x86 to ARMv5 and 88.68% when translating to RISC-V64, with correctness judged by executing the generated assembly against unit tests in an emulated environment. In a deployment case study on an Apple M2, the transpiled ARM64 binaries outperform Apple's Rosetta 2 by 1.73x in speed, 2.41x in memory efficiency, and 1.47x in energy efficiency. If true, this shows that learning-based transpilation can bridge the architectural gap between CISC and RISC instruction sets while preserving semantics and even improving performance, offering an alternative to dynamic binary translation.

What carries the argument

The central machinery is a fine-tuned autoregressive language model that learns the conditional distribution $\mathrm{P}(Y \mid X)$ over assembly tokens, where $X$ is x86 assembly and $Y$ is ARM or RISC-V assembly. The model is trained on paired outputs from compiling 500,000 C programs to x86 and ARMv5, which supplies the CISC/RISC correspondence, and an extended tokenizer keeps frequently used opcodes and register names as single tokens so the model can track them across the translation. The load-bearing evaluation is functional rather than syntactic: generated assembly is assembled and executed against unit tests in an emulator, so accuracy is measured by whether the program behaves correctly.

What would settle it

A fuzzy-duplicate search comparing the 164 HumanEval C functions against the training corpus, for example by hashing tokens of the compiled assembly or using a clone detector, would settle the claim. Finding even a few benchmark programs in the training data would make the reported accuracies look like memorization; re-running evaluation on a fresh, never-seen set of C functions with unit tests would test generalization directly.

Watch

Extended reading notes

Core claim

The paper's central discovery is that direct x86-to-ARM assembly transpilation is a learnable mapping, not a rule-engineering problem. By fine-tuning a 1.3B-parameter code language model on hundreds of thousands of C programs compiled into paired x86 and ARM assembly, and by extending the tokenizer so that opcodes and register names stay as single tokens, the authors obtain a model that generates ARM assembly preserving functional behavior on 79.25% of the benchmark programs and 88.68% for RISC-V64. They further show that correct outputs are not mere copies of ground truth: the generated code often differs syntactically yet still passes the same unit tests, with variations such as different register allocation, reordered commutative operands, and instruction consolidation. In the ARMv8 case study, the transpiled code, compiled natively, runs faster and uses less memory and energy than Rosetta 2's dynamic translation, suggesting one-time transpilation can beat virtualization.

Load-bearing premise

The reported accuracies assume that none of the 164 HumanEval evaluation programs, or close variants, appeared in the 500,000 GitHub-sourced C programs used for training, because the paper reports no decontamination check.

Editorial extensions

If this is right

  • Legacy x86 binaries whose assembly is available could be converted once into ARM or RISC-V assembly and then natively compiled, eliminating the per-run translation overhead of emulators.
  • Quantized versions at int8 and int4 precision retain most of the accuracy, so the transpiler can plausibly run on CPUs and resource-constrained devices without a GPU.
  • On Apple hardware, the transpiled code beats Rosetta 2 on speed, memory, and energy in the tested programs, suggesting that one-time offline transpilation can outperform dynamic translation where a pre-pass is feasible.
  • The same recipe extends to a second RISC target, RISC-V64, with higher accuracy, indicating the approach transfers across target ISAs rather than being hand-tuned to ARM.
  • Smaller task-specific models outperform much larger general-purpose code models on this benchmark, implying that fine-tuning and tokenization matter more than raw model size for assembly transpilation.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Editorial extension: HumanEval functions are short and compile to small assembly functions, so the 79.25% and 88.68% accuracies are likely an upper bound for large real-world binaries; a natural next test is accuracy on multi-thousand-instruction functions.
  • Editorial extension: Because the training recipe only needs paired compilations, the same method could be retargeted to other ISA pairs, for instance x86 to PowerPC or MIPS, without changing the architecture of the approach.
  • Editorial extension: The speedup over Rosetta 2 stems from replacing runtime translation with a one-time offline translation, so the performance and energy advantage could widen on long-running static workloads, although the paper does not measure that directly.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 6 minor

Summary. The paper proposes CRT, a fine-tuned 1.3B-parameter DeepSeek-Coder model that translates x86 assembly to ARMv5 and RISC-V64 assembly. Training pairs are generated by compiling 500k AnghaBench C programs with gcc and cross-compilers at -O0, and evaluation uses the 164 HumanEval C problems from LLM4Decompile, with functional correctness checked by executing the generated assembly under QEMU against unit tests. The authors report 79.25% ARMv5 and 88.68% RISC-V64 test accuracy, and on an Apple M2 Pro report that ARMv8-transpiled code achieves a 1.73x speedup, 2.41x memory efficiency, and 1.47x energy efficiency over Rosetta 2. The paper also documents tokenizer extensions, quantization studies, and an analysis of syntactic versus semantic equivalence classes.

Significance. If the results are clean, this is a solid demonstration that a small fine-tuned LLM can perform CISC-to-RISC assembly translation with functional correctness, and the QEMU-based execution oracle is a considerably stronger signal than syntactic matching alone. The public release of code, models, training data, and benchmarks is also a concrete strength. The ARMv8 case study, although under-specified, addresses a practically relevant deployment setting. The main significance of the paper depends on two fixable points: documented train/eval decontamination and clarity about which programs enter the Rosetta performance comparison. With those provided, the paper would be a useful contribution to LLM-for-code and binary-translation research.

major comments (3)
  1. [§4.1, §4.3, Tables 2–3] The paper reports the 79.25% ARMv5 and 88.68% RISC-V64 accuracies as evidence that CRT generalizes, but no decontamination step is described between the 500k AnghaBench training programs and the 164 HumanEval evaluation problems. Both corpora originate from public GitHub C code, and HumanEval is widely redistributed, so exact or near-duplicate source functions may appear in AnghaBench. Because the model is fine-tuned for two epochs on compiled x86/ARM pairs, even a few duplicated evaluation programs would allow memorization and inflate the measured accuracy. The 98.81% line coverage reported in §4.3 addresses test-suite thoroughness, not train/eval separation. The authors should report an overlap audit at both the C-source level and the compiled-assembly level, and should report all headline accuracies on the guaranteed-disjoint subset.
  2. [§7.1–7.2, Table 4, Figure 5] The Apple M2 case study is under-specified in a way that affects the headline deployment claims. Table 4 gives the ARMv8-trained model a functional accuracy of 75.0% (123/164), and Figure 5 shows that 23 programs fail only on the M2, yet §7.2 reports aggregate 1.73x speedup, 2.41x memory efficiency, and 1.47x energy efficiency with no statement of which programs were included in the geometric means. If the performance ratios are computed only over programs that CRT transpiled correctly while Rosetta ran all programs, the comparison is selection-biased. The authors should state the inclusion criterion, report the performance per program or at least for correct and incorrect subsets, and clarify that the abstract's 79.25% refers to the ARMv5 model rather than the ARMv8 model used in deployment.
  3. [§4.2, §4.4] The functional-correctness metric is the load-bearing measurement, but the evaluation procedure is not fully reproducible from the text. The paper does not specify how the generated ARM assembly is linked with the HumanEval test harness, how non-assembling or non-linking outputs are counted, whether a timeout is used under QEMU, and whether the ground-truth ARM program is compiled with the same flags and linker configuration. These details are necessary to interpret the accuracy numbers and to allow independent replication. I ask the authors to provide the exact evaluation pipeline (compile, link, QEMU invocation, pass/fail criterion) in the main text or an appendix.
minor comments (6)
  1. [Abstract and §1] The abstract reports 88.68% accuracy for RISC-V64 while the contribution list in §1 reports 88.69%; these numbers should be made consistent.
  2. [§7.1] The text says the case study uses a model 'trained on ARMv8', but the methodology in §4.1 only describes ARMv5 cross-compilation; please describe the ARMv8 training set, flags, and epochs explicitly.
  3. [Tables 2 and 3] The comparison with GPT-4o, DeepSeekCoder2-16B, and Yi-Coder-9B lacks the prompting protocol and decoding settings; without this information, the '9.8x accuracy' claim overstates the significance of the comparison.
  4. [§4.3 and Abstract] Calling the 164-problem HumanEval C suite a 'comprehensive test suite' is an overstatement; the authors should either add more diverse benchmarks or soften the wording.
  5. [Figure 4] In the manuscript text, Figure 4 appears as a sequence of unicode placeholders rather than readable axis labels; please ensure the actual PDF contains legible figures and captions.
  6. [§3.2] The statement that 500k samples correspond to 8 billion tokens is not obviously consistent with the reported average of 13k tokens per sample; please clarify whether the count includes both source and target assembly tokens.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: headline accuracies are externally measured on HumanEval; self-cited GUESS & SKETCH is a baseline, not a load-bearing premise.

full rationale

CRT's central claims are empirical: a fine-tuned 1.3B model is scored by executing its generated ARM/RISC-V assembly against HumanEval test cases under QEMU, and M2 performance is measured against Rosetta. No equation defines the prediction in terms of the fitted parameters, and no fitted parameter is renamed as a prediction. The only author-overlapping citation is Lee et al. (GUESS & SKETCH), used as prior-work baseline and motivation for the BART alignment experiment; the headline results come from DeepSeek-Coder with a custom tokenizer and do not depend on that citation. The train/evaluation pipeline does share the same gcc -O0 compilation flow, and the paper reports no decontamination between AnghaBench and HumanEval; that is a potential validity threat (memorization rather than generalization), but it is a data-separation issue, not a circular derivation. The ARMv5 versus ARMv8 accuracy difference and Rosetta comparison are measurements with stated setups. I find no circular step reducible by construction or self-citation.

Assumptions & free parameters 5 free parameters · 4 assumptions · 0 invented entities

The central claim rests on the paired-assembly training setup and the HumanEval evaluation protocol. No new physical entities are introduced; the key assumptions are data-level (disjointness, representativeness) and oracle-level (QEMU correctness, test-suite sufficiency).

free parameters (5)
  • beam size = not stated for main results
    Figure 3a shows accuracy rises from about 72% to 79% as beam size increases from 1 to 8; the headline 79.25% is tied to an unspecified decoding choice.
  • training data size = 500k AnghaBench programs
    Accuracy improves with dataset size (Figure 3b); the reported numbers correspond to this arbitrary cutoff rather than a converged or principled choice.
  • optimization level = -O0
    All training and evaluation data are compiled at -O0 (Section 4.1, 4.2); the accuracy and performance claims do not extend to other optimization levels.
  • quantization level = int8 or int4 in deployment
    ARMv5 accuracy drops from 79.25% (float32) to 72.96% (int4); RISC-V accuracy drops from 88.68% to 68.55% (int4), so reported accuracy depends on the deployment precision.
  • context window = 16k tokens
    Chosen to fit larger assembly functions and to track register usage (Section 4.2); the model's behavior is sensitive to this capacity.
assumptions (4)
  • domain assumption Training on compiler-generated assembly pairs from identical C source yields a general x86-to-ARM transpilation function.
    The dataset (Section 4.1) is generated by compiling each C program with gcc -O0 and arm-linux-gnueabi-gcc -O0; the model never sees hand-written assembly or disassembled binaries.
  • domain assumption The HumanEval evaluation set is disjoint from the AnghaBench training set.
    No decontamination is reported (Sections 4.1 and 4.3); both corpora are drawn from public GitHub C code, so overlap is possible.
  • domain assumption Passing HumanEval unit tests under QEMU is a sufficient oracle for transpilation correctness.
    A transpilation is considered correct if it passes all test cases of the program (Section 4.4); this equates correctness with the provided test suite rather than exhaustive semantic equivalence.
  • domain assumption QEMU faithfully emulates ARMv5 and RISC-V64 for the evaluated programs.
    QEMU is the verification environment for the reported accuracy numbers (Sections 4.2 and 5).

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Cite this review

Pith. "Pith review of From CISC to RISC: language-model guided assembly transpilation." pith.science (2026). https://pith.science/paper/G5C6XJRS

@misc{pith2026241116341,
  author       = {Pith},
  title        = {Pith review of: From CISC to RISC: language-model guided assembly transpilation},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/G5C6XJRS}},
  note         = {Machine review of arXiv:2411.16341}
}
abstract

The transition from x86 to ARM architecture is becoming increasingly common across various domains, primarily driven by ARM's energy efficiency and improved performance across traditional sectors. However, this ISA shift poses significant challenges, mainly due to the extensive legacy ecosystem of x86 software and lack of portability across proprietary ecosystems and software stacks. This paper introduces CRT, a lightweight LLM-based transpiler that automatically converts x86 assembly to ARM assembly. Our approach bridges the fundamental architectural gap between x86's CISC-based and ARM's RISC-based computing paradigms while preserving program semantics and optimizing performance. We evaluate CRT on diverse real-world applications, achieving 79.25% translation accuracy from x86 to ARMv5 on our comprehensive test suite, and an 88.68% accuracy from x86 to RISC-V. In practical deployments on Apple M2 hardware (ARMv8), our transpiled code achieves 1.73$\times$ speedup compared to Apple's Rosetta 2 virtualization engine, while delivering 2.41$\times$ memory efficiency and 1.47$\times$ better energy consumption. Through testing and analysis, we show that CRT successfully navigates the CISC/RISC divide and generates correctly executable RISC code despite machine ``language'' barriers. We release our code, models, training datasets, and benchmarks at: \url{https://ahmedheakl.github.io/asm2asm/}.

Figures

Figures reproduced from arXiv: 2411.16341 by the authors.

Figure 1
Figure 1. Conceptual representation of an asm-to-asm transpiler, which would enable direct “translation” from one machine language to another without needing the source code and by-passing the software stack [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗
Figure 2
Figure 2. CRT pipeline stages: Data (AnghaBench data curation), Experimentation (model tuning and accuracy), and Optimization & Deployment (final training and Rosetta evaluation). 3.1 Problem Definition We aim to translate x86 assembly code to ARM assembly code by leveraging Language Models (LMs) to automat￾ically handle the fundamental differences between these ISAs. Let X ={x1,x2,...,xn} denote the set of x86 vocab, and Y =… view at source ↗
Figure 3
Figure 3. DeepSeek-1.3B performance: (a) Accuracy across beam sizes (1, 2, 4, 8) for different training data sizes. (b) Accuracy progression over training steps with a logarithmic trend. (c) Quantization impact (float32, bfloat16, int8, int4) on ARM and RISC-V64. notably improved the model’s edit distance, decreasing it by 8%. This improvement is attributed to enhanced convergence and training stability, which are crucial for… view at source ↗
Figures from the paper (3 more)
Figure 4
Figure 4. Figure 4: Measured execution time, energy utilization, and RAM usage across different settings on Apple M2 Macbook. A key finding is that compared to ARMv5, we observed a performance drop of 4.25% with ARMv8 achieving 75.0% on the evaluation-set. This decline can be attributed t…
Figure 5
Figure 5. Figure 5: Confusion matrix of the proposed approach executed on QEMU (ARMv5) and M2 (ARMv8) for HumanEval programs. Examining the confusion matrix ( [PITH_FULL_IMAGE:figures/full_fig_p010_5.png]
Figure 6
Figure 6. Figure 6: Example Assembly Code Generated from Identical Source Program for x86, ARMv5, and ARMv8, with aligned assembly segments highlighted by functionality. A.2 Assembly Code Comparison Across Architectures [PITH_FULL_IMAGE:figures/full_fig_p015_6.png]

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