Pith. sign in

REVIEW 5 major objections 8 minor 41 references

Core Placement Optimization of Many-core Brain-Inspired Near-Storage Systems for Spiking Neural Network Training

T0 review · 5 major / 8 minor · reviewed 2026-08-12 · deepseek-v4-flash

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗ Review JSON

Pith's one-line read A reinforcement-learning placement method cut simulated inter-core communication during spiking neural network training by up to 32.92%, beating Zigzag, Sigmate, random search, and Policy baselines.

desk verdict A sensible extension of RL-based core placement to SNN training, but the headline numbers are projections through an unverified linearity assumption. read the letter →

arxiv 2411.19430 v2 pith:VYM5RE2W submitted 2024-11-29 cs.AR cs.NE

Xueke Zhu (1) , Wenjie Lin (1) , Yanyu Lin (1) , Yunhao Ma (1)(3) , Wenxiang Cheng (1) , Zhengyu Ma (1) , Yonghong Tian (1 , 2)
show 4 more authors
Huihui Zhou (1) ((1) Pengcheng Laboratory (2) Peking University (3) Southern University of Science Technology)
This is my paper · ORCID
classification cs.ARcs.NE
keywords spikingneuralnetworksSNNtrainingcoreplacementreinforcementlearningmany-corearchitecturenear-memorycomputingdeploymentoptimizationgraphconvolution
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper claims that mapping the logical cores of a spiking neural network (SNN) training workload onto a many-core near-memory chip is a combinatorial optimization problem that can be solved with deep reinforcement learning better than with heuristics. It proposes a three-part method: a balanced partitioning that splits each layer unevenly along input and output channels to equalize computation and storage latency; an actor-critic policy network that takes the logical graph and the chip's on-chip network topology as inputs and outputs a placement via continuous values discretized to physical cores; and an FPDeep-style fine-grained pipeline that overlaps computation between layers. On a simulated 32-core system, the method reports training communication cost reduced by 28.84% (Spike-ResNet18), 32.92% (Spike-VGG16), and 18.89% (Spike-ResNet50) relative to Zigzag, Sigmate, random search, and the Policy baseline, with similar gains on 64 cores. The sympathetic reading is that reinforcement-learning-based placement, previously applied to inference, can also cut communication and improve utilization during the more demanding training phase.

What carries the argument

The load-bearing mechanism is an off-policy deterministic actor-critic framework with a graph-convolutional policy network. The logical SNN graph and the physical on-chip network topology are encoded as features; the actor outputs continuous coordinates for each logical core, which are clipped and discretized to physical core positions, with ties broken by a clockwise shortest-path search. The reward is a function of inter-core communication data volume only, based on the assumption that power and delay are linear in communication cost. A balanced partitioning step splits each layer along input and output channels so that per-core computation plus storage transmission time is balanced, and an FPDeep-style pipeline overlaps layer computations to raise core utilization.

What would settle it

Measure wall-clock training time and chip power on a physical or cycle-accurately calibrated many-core near-memory system running Spike-ResNet18, Spike-VGG16, and Spike-ResNet50 with the proposed placement versus Zigzag. If the training-time and power reductions are substantially smaller than the communication-cost reductions (28.84%, 32.92%, 18.89%), the linear-reward assumption that carries the argument is false.

Watch

Extended reading notes

Core claim

The central claim is that SNN training deployment on many-core near-memory systems can be optimized by treating placement as a graph-aware reinforcement learning problem and by balancing both computation and storage when partitioning the model. The paper reports that its deployment scheme reduces training communication cost by 28.84% for Spike-ResNet18, 32.92% for Spike-VGG16, and 18.89% for Spike-ResNet50 on a 32-core simulated architecture, outperforming Zigzag, Sigmate, random search, and the Policy baseline; the method also generalizes to 64 cores and improves ANN inference placement, beating Policy by 6.5% in average communication cost. Because power consumption and delay are assumed linear in communication cost, these communication reductions are presented as reductions in training time and chip power.

Load-bearing premise

The results assume that power consumption and delay are linear in inter-core communication cost, so the reward function only needs to minimize communication; if that linearity does not hold, the reported training-time and power reductions would not follow from the measured communication savings.

Editorial extensions

If this is right

  • If correct, SNN training on many-core near-memory chips becomes more feasible: communication-heavy training can be mapped to reduce data movement and hotspot formation.
  • The method extends beyond SNNs: the same placement approach improves ANN inference on a Tianjic-like architecture, beating the Policy baseline by 6.5%.
  • The approach scales from 32 to 64 cores with communication cost reduced by more than 22.64%, suggesting it generalizes to larger many-core systems.
  • Fine-grained pipelining combined with placement increases the number of cores computing simultaneously, improving utilization and shortening training clock cycles.
  • Better placement reduces average hop count (by 0.67 per packet vs Zigzag), which should lower both latency and energy per transmission.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The paper's reported training-time and power gains rest on the unverified linear relation between communication cost, delay, and power; on hardware where compute or off-chip memory dominates, the placement gains would be smaller than claimed.
  • The clockwise shortest-path routing assumption is static; under adaptive or congestion-aware routing, the placement optimized for one routing policy may not be optimal, so the method's gains are routing-policy-dependent.
  • A direct test on a physical many-core near-memory prototype, measuring wall-clock training time and power rather than simulated communication cost, would settle whether the linearity assumption holds.
Share X Bluesky LinkedIn Reddit HN

Signed reviews

No signed human review yet.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

5 major / 8 minor

Summary. The paper proposes a deep reinforcement learning method for physical core placement of spiking neural network training workloads on a many-core near-memory architecture, combined with a balanced storage/computation partitioning method and FPDeep-style pipelining. The authors evaluate on simulated 32-core and 64-core systems with Spike-ResNet18, Spike-VGG16, and Spike-ResNet50, reporting reductions in communication cost, latency, hop count, and improved throughput relative to Zigzag, Sigmate, random search, and Policy. The central claim is that the method reduces SNN training time and power consumption by optimizing inter-core communication.

Significance. If the results hold, the paper addresses an important problem—mapping logical SNN training graphs to physical many-core systems—and would extend RL-based placement from inference to training. The use of graph convolution to encode the logical graph and architecture topology is a reasonable and potentially impactful approach, and the idea of jointly optimizing partitioning and placement is credible. The paper also provides useful comparison against existing placement methods and visualizes hotspot reduction. However, the significance is tempered by the fact that the headline gains in latency and power are not directly measured but projected through an unverified linear relationship with communication cost, and the simulator is unreleased.

major comments (5)
  1. [Section 4.3 (Reward), Eq. (4)] The assertion that 'power consumption and delay are linear with respect to communication cost' is load-bearing for the paper's central claims. The reported latency reductions (Section 5.2, Figures 6(b)-6(c), 8(b)) and the promised power reduction (Abstract, Conclusion) are not direct measurements but consequences of this assumption. No derivation, measurement, or citation is provided for this linear relation, and the statement 'the reward function of Actor Network only needs to consider the communication between computing cores' does not follow from linearity alone. Moreover, Eq. (4) is not readable: the terms in the max expression are placeholders (??????? etc.) and are never defined, so the reward is not reproducible. The authors should either measure delay and power directly in the simulator or provide empirical evidence (e.g., scatter plots of delay/power vs. communication cost for representative mappings) that the linear model holds.
  2. [Sections 3.3 and 4.3 vs. Abstract and Section 5.1] The algorithm identity is inconsistent. The abstract and Section 5.1 state 'Off-policy Deterministic Actor-Critic' and 'based on DDPG', while Section 3.3 says 'We employ the Proximal Policy Optimization (PPO) algorithm' and Section 4.3 says 'optimizing the surrogate loss with PPO'. DDPG and PPO are distinct algorithms, and the update rule in Eq. (5) resembles PPO's clipped surrogate, not DDPG. The paper should state clearly which algorithm is implemented, reconcile the terminology (including 'near-end policy optimization' in the abstract), and specify how the Actor-Critic architecture with graph convolution is trained under the chosen algorithm.
  3. [Section 5.1 and Figures 6-8] The evaluation lacks error bars or multiple-seed reporting for the RL method. Because the policy is stochastic and the discretization/collision-resolution procedure introduces randomness, the reported improvements (e.g., 28.84%, 32.92%, 18.89% training communication cost reduction) could be seed-dependent or tuned. At minimum, the authors should report mean and standard deviation over at least 5 random seeds for each model and core count. In addition, the simulator is not released, and no validation against RTL simulation or a hardware prototype is described, so the absolute values in Figures 6-8 cannot be externally checked; the paper should include a description of the simulator's accuracy or make it available.
  4. [Section 5.2 (metric independence and circularity)] The reward function is communication cost, and the headline evaluation metric is also communication cost (Figures 6(a), 8(a)). While the paper also reports latency, throughput, and hop distance, these are said to be reduced as a consequence of the same linear assumption, rather than measured independently. To break the circularity, the simulator should report cycle-accurate latency and energy/power directly for the final placements, and ideally rank placements by those metrics without reference to the reward proxy. Please also clarify in the text which quantities are measured and which are derived from the linear model.
  5. [Section 5.2 and Figure 9] The paper claims that the FPDeep-style pipelining 'significantly reduc[es] model training time' and improves utilization, but Figure 9 only shows qualitative waveforms of core utilization and does not report training time or throughput numbers with and without pipelining. Since 'reducing model training time' is part of the central claim, the evaluation should include quantitative end-to-end training latency or cycles for the layer-wise vs. FPDeep pipelines, ideally combined with the proposed placement.
minor comments (8)
  1. [Abstract] The phrase 'near-end policy optimization' should read 'proximal policy optimization'.
  2. [Equation (4)] Equation (4) contains undefined placeholders; the variables should be spelled out and the connection between the reward text and the equation made explicit.
  3. [Table 1] The acronym 'EER' is introduced without definition; it likely means 'energy efficiency ratio,' and the units (fps/W) suggest so. Please define it at first use.
  4. [Section 3.1] Definitions A-C contain garbled mathematical symbols (e.g., '???'); please typeset all definitions properly.
  5. [Section 5.2, line near Figures 6(b)-6(c)] The sentence 'the latency and throughput of the proposed method is reduced by about 8%' is contradictory; throughput should increase while latency decreases. Please correct.
  6. [Figure 9 caption] The caption 'The computing resource usage Layer-wise and FPDeep' is missing prepositions; also, the figure panels are not all referenced in the text with sufficient detail.
  7. [Section 5.3] The sentence 'which is 0.167 less than the average transmission distance of single data packet of the Policy method' is redundant with the preceding number; please tighten.
  8. [References] References [32] and [33] appear mis-ordered in the text: SemiMap is described after Prime, but the citation [32] points to TrueNorth in the reference list; verify the citation numbering.

Circularity Check

1 steps flagged · score 6.0 of 10

One load-bearing prediction is circular: Section 4.3 defines delay/power as linear in communication cost and the reward as communication cost, so the reported latency and power reductions are rescalings of the optimized objective rather than independent results; the communication-versus-heuristic comparison is independent.

  1. self definitional [Section 4.3 (Reward) and Section 5.2 (Figures 6b-6c, 8b-8c; Conclusion)]
    "The power consumption and delay are linear with respect to communication cost, so the reward function of Actor Network only needs to consider the communication between computing cores."

    Section 4.3 makes delay and power deterministic linear functions of communication cost, and Eq. (4) defines the reward as the negative of inter-core communication. Section 5.2 then reports communication reductions of 28.84%, 32.92%, and 18.89%, and separately claims latency reduced by about 10% and throughput improved, while the abstract and conclusion promise reduced training time and power. Under the paper's own linearity premise, the latency, throughput, and power numbers are constant multiples of the optimized communication objective, so those predictions are equivalent to the reward by construction. The communication-cost improvements against fixed heuristics (Zigzag, Sigmate, RS, Policy) are independent evidence, which is why the circularity is partial rather than total.

full rationale

No self-citation chain or imported uniqueness theorem is load-bearing; the method builds on external work (Policy, FPDeep) and is compared against fixed heuristics. The core optimization of communication cost is a legitimate objective, and the communication comparisons have independent content. The circular element is the extension from the communication reward to the headline training-time and power claims: the paper itself asserts that delay and power are linear in communication cost, so those reported gains are rescaled versions of the quantity being optimized rather than independently measured end-to-end results. A cycle-level simulator produced all numbers and is unreleased, so the linearity bridge cannot be checked externally. This yields a partial-circularity score of 6 rather than a higher score, because the raw communication objective and the baselines remain meaningful.

Assumptions & free parameters 2 free parameters · 5 assumptions · 0 invented entities

The central claim rests on a custom simulator, a linearity assumption, and hand-picked RL hyperparameters. No new physical entities are introduced; the contribution is a new mapping and partitioning method.

free parameters (2)
  • RL training hyperparameters = learning_rate=0.005, batch_size=256, ppo_epoch=10, ppo_clip=0.5, feature_size=32, reward_clip=[-10,10]
    Reported in Section 5.1 but chosen by hand; no sensitivity analysis is given, so the reported gains could depend on this tuning.
  • Number of logical cores per model = 32 and 64
    The paper segments each model into 32 or 64 logical cores; the partition granularity is chosen by the authors and is not swept, even though it affects graph size and communication patterns.
assumptions (5)
  • domain assumption Power consumption and delay are linear in communication cost between cores.
    Stated in Section 4.3, Reward paragraph; used to justify a reward that considers only communication cost, yet no derivation or measurement is provided.
  • domain assumption The custom many-core near-memory simulator faithfully models the proposed architecture, routing, and SNN training dataflow.
    Section 5.1 says all results are from simulator evaluation; the simulator is not released or validated against hardware or a public benchmark.
  • domain assumption Clockwise-search shortest-path routing is an accurate model of the target NoC routing policy.
    Section 3.2 introduces this routing model; hop count and communication cost results depend on it.
  • domain assumption The logical graph node features (degree, data volume, multicast flag) are sufficient for the policy to learn good placements.
    Section 4.3 defines five node features as the environment state; no feature ablation is reported.
  • standard math Standard PPO clipping and policy gradient convergence assumptions hold for this discrete placement problem.
    Section 3.3 and Eq. 5 rely on PPO's clipped surrogate objective without adaptation proof for the collision-removal discretization step.

how reviews work

0 comments
Cite this review

Pith. "Pith review of Core Placement Optimization of Many-core Brain-Inspired Near-Storage Systems for Spiking Neural Network Training." pith.science (2026). https://pith.science/paper/VYM5RE2W

@misc{pith2026241119430,
  author       = {Pith},
  title        = {Pith review of: Core Placement Optimization of Many-core Brain-Inspired Near-Storage Systems for Spiking Neural Network Training},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/VYM5RE2W}},
  note         = {Machine review of arXiv:2411.19430}
}
read the original abstract

With the increasing application scope of spiking neural networks (SNN), the complexity of SNN models has surged, leading to an exponential growth in demand for AI computility. As the new generation computing architecture of the neural networks, the efficiency and power consumption of distributed storage and parallel computing in the many-core near-memory computing system have attracted much attention. Among them, the mapping problem from logical cores to physical cores is one of the research hotspots. In order to improve the computing parallelism and system throughput of the many-core near-memory computing system, and to reduce power consumption, we propose a SNN training many-core deployment optimization method based on Off-policy Deterministic Actor-Critic. We utilize deep reinforcement learning as a nonlinear optimizer, treating the many-core topology as network graph features and using graph convolution to input the many-core structure into the policy network. We update the parameters of the policy network through near-end policy optimization to achieve deployment optimization of SNN models in the many-core near-memory computing architecture to reduce chip power consumption. To handle large-dimensional action spaces, we use continuous values matching the number of cores as the output of the policy network and then discretize them again to obtain new deployment schemes. Furthermore, to further balance inter-core computation latency and improve system throughput, we propose a model partitioning method with a balanced storage and computation strategy. Our method overcomes the problems such as uneven computation and storage loads between cores, and the formation of local communication hotspots, significantly reducing model training time, communication costs, and average flow load between cores in the many-core near-memory computing architecture.

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

41 extracted references · 32 canonical work pages

  1. [1]

    Tensorflow: A system for large-scale machine learning

    A Agarwal, P Barham, E Brevdo, et al. Tensorflow: A system for large-scale machine learning. In Proceedings of the 12th USENIX Conference on Operating Systems Design and Implementation. USENIX Association, 2016

    work page 2016

  2. [2]

    Pytorch: An imperative style, high-performance deep learning library

    Adam Paszke, Sam Gross, Francisco Massa, et al. Pytorch: An imperative style, high-performance deep learning library. Advances in neural information processing systems, 32, 2019

    work page 2019

  3. [3]

    Delving deep into rectifiers: Surpassing human-level performance on imagenet classification

    Kaiming He, Xiangyu Zhang, Shaoqing Ren, and Jian Sun. Delving deep into rectifiers: Surpassing human-level performance on imagenet classification. In Proceedings of the IEEE international conference on computer vision, pages 1026–1034, 2015

    2015

  4. [4]

    Deep neural networks are more accurate than humans at detecting sexual orientation from facial images

    Yilun Wang and Michal Kosinski. Deep neural networks are more accurate than humans at detecting sexual orientation from facial images. Journal of personality and social psychology, 114(2):246, 2018

    work page 2018

  5. [5]

    Towards endto-end speech recognition with deep convolutional neural networks

    Ying Zhang, Mohammad Pezeshki, Philémon Brakel, et al. Towards endto-end speech recognition with deep convolutional neural networks. arXiv preprint arXiv:1701.02720, 2017

    arXiv 2017

  6. [6]

    Sequence to sequence learning with neural networks

    Ilya Sutskever, Oriol Vinyals, and Quoc V Le. Sequence to sequence learning with neural networks. Advances in neural information processing systems, 27, 2014

    2014

  7. [7]

    Core placement optimization for multichip many-core neural network systems with reinforcement learning

    Nan Wu, Lei Deng, Guoqi Li, and Yuan Xie. Core placement optimization for multichip many-core neural network systems with reinforcement learning. ACM Transactions on Design Automation of Electronic Systems (TODAES), 26(2):1–27, 2020

    work page 2020

  8. [8]

    Towards spike-based machine intelligence with neuromorphic computing

    Kaushik Roy, Akhilesh Jaiswal, and Priyadarshini Panda. Towards spike-based machine intelligence with neuromorphic computing. Nature, 575(7784):607–617, 2019

    2019

Show all 41 references
  1. [9]

    A wafer-scale neuromorphic hardware system for large-scale neural modeling

    Johannes Schemmel, Daniel Brüderle, Andreas Grübl, et al. A wafer-scale neuromorphic hardware system for large-scale neural modeling. In 2010 IEEE International Symposium on Circuits and Systems (ISCAS), pages 1947–1950. IEEE, 2010

    2010

  2. [10]

    A reconfigurable on-line learning spiking neuromorphic processor comprising 256 neurons and 128k synapses

    Ning Qiao, Hesham Mostafa, Federico Corradi, et al. A reconfigurable on-line learning spiking neuromorphic processor comprising 256 neurons and 128k synapses. Frontiers in neuroscience, 9:141, 2015

    2015

  3. [11]

    A 0.086-mm ^212.7- pj/sop 64k-synapse 256-neuron online-learning digital spiking neuromorphic processor in 28-nm cmos

    Charlotte Frenkel, Martin Lefebvre, Jean-Didier Legat, and David Bol. A 0.086-mm ^212.7- pj/sop 64k-synapse 256-neuron online-learning digital spiking neuromorphic processor in 28-nm cmos. IEEE transactions on biomedical circuits and systems, 13(1):145–158, 2018

    2018

  4. [12]

    Loihi: A neuromorphic manycore processor with on-chip learning

    Mike Davies, Narayan Srinivasa, Tsung-Han Lin, et al. Loihi: A neuromorphic manycore processor with on-chip learning. Ieee Micro, 38(1):82–99, 2018

    2018

  5. [13]

    H2learn: High-efficiency learning accelerator for high-accuracy spiking neural networks

    Ling Liang, Zheng Qu, Zhaodong Chen, et al. H2learn: High-efficiency learning accelerator for high-accuracy spiking neural networks. IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems, 41(11):4782–4796, 2021

    2021

  6. [14]

    Tianjic: A unified and scalable chip bridging spike-based and continuous neural computation[J]

    Deng Lei, Wang Guanrui , Li Guoqi, et al. Tianjic: A unified and scalable chip bridging spike-based and continuous neural computation[J]. IEEE Journal of Solid-State Circuits, 2020, 55(8): 2228-2246

    2020

  7. [15]

    Towards artificial general intelligence with hybrid tianjic chip architecture

    Jing Pei, Lei Deng, Sen Song, et al. Towards artificial general intelligence with hybrid tianjic chip architecture. Nature, 572(7767):106–111, 2019

    2019

  8. [16]

    Policy gradient-based core placement optimization for multichip many-core systems

    Wooshik Myung, Donghyun Lee, Chenhang Song, et al. Policy gradient-based core placement optimization for multichip many-core systems. IEEE Transactions on Neural Networks and Learning Systems, 2021

    2021

  9. [17]

    Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks

    Yu-Hsin Chen, Tushar Krishna, Joel S Emer, and Vivienne Sze. Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks. IEEE journal of solid-state circuits, 52(1):127–138, 2016

    2016

  10. [18]

    Understanding reuse, performance, and hardware cost of dnn dataflow: A data-centric approach

    Hyoukjun Kwon, Prasanth Chatarasi, Michael Pellauer, et al. Understanding reuse, performance, and hardware cost of dnn dataflow: A data-centric approach. In Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, pages 754–768, 2019

    2019

  11. [19]

    Timeloop: A systematic approach to dnn accelerator evaluation

    Angshuman Parashar, Priyanka Raina, Yakun Sophia Shao, et al. Timeloop: A systematic approach to dnn accelerator evaluation. In 2019 IEEE international symposium on performance analysis of systems and software (ISPASS), pages 304–315. IEEE, 2019

    2019

  12. [20]

    Dnn dataflow choice is overrated

    Xuan Yang, Mingyu Gao, Jing Pu, Ankita Nayak, Qiaoyi Liu, Steven Emberton Bell, Jeff Ou Setter, Kaidi Cao, Heonjae Ha, Christos Kozyrakis, et al. Dnn dataflow choice is overrated. arXiv preprint arXiv:1809.04070, 6:5, 2018

    2018 arXiv

  13. [21]

    Heterogeneous fpga-based cost-optimal design for timing-constrained cnns

    Weiwen Jiang, Edwin Hsing-Mean Sha, Qingfeng Zhuge, et al. Heterogeneous fpga-based cost-optimal design for timing-constrained cnns. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37(11):2542–2554, 2018

    2018

  14. [22]

    Xfer: A novel design to achieve super-linear performance on multiple fpgas for real-time ai

    Weiwen Jiang, Xinyi Zhang, Edwin H-M Sha, et al. Xfer: A novel design to achieve super-linear performance on multiple fpgas for real-time ai. In Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pages 305– 305, 2019

    2019

  15. [23]

    A high performance fpga-based accelerator for large-scale convolutional neural networks

    Huimin Li, Xitian Fan, Li Jiao, et al. A high performance fpga-based accelerator for large-scale convolutional neural networks. In 2016 26th International Conference on Field Programmable Logic and Applications (FPL), pages 1–9. IEEE, 2016

    2016

  16. [24]

    Confuciux: Autonomous hardware resource assignment for dnn accelerators using reinforcement learning

    Sheng-Chun Kao, Geonhwa Jeong, and Tushar Krishna. Confuciux: Autonomous hardware resource assignment for dnn accelerators using reinforcement learning. In 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pages 622–636. IEEE, 2020

    2020

  17. [25]

    Fpdeep: Scalable acceleration of cnn training on deeply-pipelined fpga clusters

    Tianqi Wang, Tong Geng, Ang Li, Xi Jin, and Martin Herbordt. Fpdeep: Scalable acceleration of cnn training on deeply-pipelined fpga clusters. IEEE Transactions on Computers, 69(8):1143– 1158, 2020

    2020

  18. [26]

    Flexlearn: fast and highly efficient brain simulations using flexible on-chip learning

    Eunjin Baek, Hunjun Lee, Youngsok Kim, and Jangwoo Kim. Flexlearn: fast and highly efficient brain simulations using flexible on-chip learning. In Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, pages 304–318, 2019

    2019

  19. [27]

    Gpipe: Efficient training of giant neural networks using pipeline parallelism

    Yanping Huang, Youlong Cheng, Ankur Bapna, et al. Gpipe: Efficient training of giant neural networks using pipeline parallelism. Advances in neural information processing systems, 32, 2019

    2019

  20. [28]

    Deep gradient compression: Reducing the communication bandwidth for distributed training

    Yujun Lin, Song Han, Huizi Mao, Yu Wang, and William J Dally. Deep gradient compression: Reducing the communication bandwidth for distributed training. arXiv preprint arXiv:1712.01887, 2017

    2017 arXiv

  21. [29]

    Deep learning with limited numerical precision

    Suyog Gupta, Ankur Agrawal, Kailash Gopalakrishnan, and Pritish Narayanan. Deep learning with limited numerical precision. In International conference on machine learning, pages 1737–1746. PMLR, 2015

    2015

  22. [30]

    Split learning for health: Distributed deep learning without sharing raw patient data

    Praneeth Vepakomma, Otkrist Gupta, Tristan Swedish, and Ramesh Raskar. Split learning for health: Distributed deep learning without sharing raw patient data. arXiv preprint arXiv:1812.00564, 2018

    2018 arXiv

  23. [31]

    Prime: A novel processing-in-memory architecture for neural network computation in reram-based main memory

    Ping Chi, Shuangchen Li, Cong Xu, et al. Prime: A novel processing-in-memory architecture for neural network computation in reram-based main memory. ACM SIGARCH Computer Architecture News, 44(3):27–39, 2016

    2016

  24. [32]

    Truenorth: Design and tool flow of a 65 mw 1 million neuron programmable neurosynaptic chip

    Filipp Akopyan, Jun Sawada, Andrew Cassidy, et al. Truenorth: Design and tool flow of a 65 mw 1 million neuron programmable neurosynaptic chip. IEEE transactions on computer-aided design of integrated circuits and systems, 34(10):1537–1557, 2015

    2015

  25. [33]

    Semimap: A semifolded convolution mapping for speed-overhead balance on crossbars

    Lei Deng, Ling Liang, Guanrui Wang, et al. Semimap: A semifolded convolution mapping for speed-overhead balance on crossbars. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 39(1):117–130, 2018

    2018

  26. [34]

    Rql: Global placement via relaxed quadratic spreading and linearization

    Natarajan Viswanathan, Gi-Joon Nam, Charles J Alpert, et al. Rql: Global placement via relaxed quadratic spreading and linearization. In Proceedings of the 44th annual Design Automation Conference, pages 453–458, 2007

    2007

  27. [35]

    Reinforcement learning for combinatorial optimization: A survey

    Nina Mazyavkina, Sergey Sviridov, Sergei Ivanov, and Evgeny Burnaev. Reinforcement learning for combinatorial optimization: A survey. Computers & Operations Research, 134:105400, 2021

    2021

  28. [36]

    Placement in integrated circuits using cyclic reinforcement learning and simulated annealing

    Dhruv Vashisht, Harshit Rampal, Haiguang Liao, Yang Lu, Devika Shanbhag, Elias Fallon, and Levent Burak Kara. Placement in integrated circuits using cyclic reinforcement learning and simulated annealing. arXiv preprint arXiv:2011.07577, 2020

    2011 arXiv

  29. [37]

    Fr¨oning

    Schindler G, Zöhrer M, Pernkopf F, Pernkopf, and H. Fr¨oning. Towards efficient forward propagation on resource-constrained systems[C]//Machine Learning and Knowledge Discovery in Databases: European Conference, ECML PKDD 2018, Dublin, Ireland, September 10–14, 2018, Proceedin...

    2018

  30. [38]

    Device placement optimization with reinforcement learning

    Azalia Mirhoseini, Hieu Pham, Quoc V Le, et al. Device placement optimization with reinforcement learning. In International Conference on Machine Learning, pages 2430–2439. PMLR, 2017

    2017

  31. [39]

    Spotlight: Optimizing device placement for training deep neural networks

    Yuanxiang Gao, Li Chen, and Baochun Li. Spotlight: Optimizing device placement for training deep neural networks. In International Conference on Machine Learning, pages 1676–1684. PMLR, 2018

    2018

  32. [40]

    Post: Device placement with cross-entropy minimization and proximal policy optimization

    Yuanxiang Gao, Li Chen, and Baochun Li. Post: Device placement with cross-entropy minimization and proximal policy optimization. Advances in neural information processing systems, 31, 2018

    2018

  33. [41]

    Baechi: fast device placement of machine learning graphs

    Beomyeol Jeon, Linda Cai, Pallavi Srivastava, et al. Baechi: fast device placement of machine learning graphs. In Proceedings of the 11th ACM Symposium on Cloud Computing, pages 416–430, 2020

    2020

Pith tools

Reviewed August 12, 2026 · model on record in the stance chip above.