Typed states for the displayed outbound observations.
Source: paper_references, paper_reference_links
Paper Citation Record · LEDGER
Instruction Scheduling in the Saturn Vector Unit
As of 9 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 3 inbound Pith citation observations for arXiv:2412.00997.
A citation records a reference. It does not transfer a finding from one paper to another.
Coverage vector
One-hop event checks from named stored sources.
Source: scholarly_work_events, retraction_status_cache, observed 2026-08-09T06:31:02.800959+00:00
Pith citing papers itemized under the disclosed page cap.
Source: paper_references, paper_reference_links, observed 2026-08-06T20:55:36.881946Z
A source-named dated measurement, never combined with another source.
Source: arxiv_reference, observed 2026-05-11T20:21:09.866582Z
Reference resolution
0 of 0 outbound references displayed
- verified exact0
- verified fuzzy0
- unresolved0
- parse uncertain0
- malformed identifier0
- metadata mismatch0
External citation measurements
No source-named external measurement is stored.
Outbound references
No outbound reference observations are available for this paper version.
Pith citing papers
Observation 5339ec5c-3b1b-46f8-abf2-5ac2197e3fb0 · inbound
Tensor Program Optimization for the RISC-V Vector Extension Using Probabilistic Programs cites this paper.
Tensor Program Optimization for the RISC-V Vector Extension Using Probabilistic Programs Instruction Scheduling in the Saturn Vector Unit
Reference 3
- Resolution
- unresolved
- no resolver link, observed 2026-08-06T20:55:36.881946Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 09afaba6-c013-4d72-b61e-e1f8f1083eb7 · inbound
Microarchitectural Co-Optimization for Sustained Throughput of RISC-V Multi-Lane Chaining Vector Processors cites this paper.
Microarchitectural Co-Optimization for Sustained Throughput of RISC-V Multi-Lane Chaining Vector Processors Instruction Scheduling in the Saturn Vector Unit
Reference 24
- Resolution
- verified exact
- arxiv_id, observed 2026-05-11T20:21:09.869274Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.
Observation 6ba8c9f3-723c-464b-9472-c3f70a0e2a45 · inbound
SEAM-V: A Hybrid-Decoupled RISC-V Vector Processor with Backend-Visible Packet Semantics and Source-Lifetime-Aware Scheduling cites this paper.
SEAM-V: A Hybrid-Decoupled RISC-V Vector Processor with Backend-Visible Packet Semantics and Source-Lifetime-Aware Scheduling Instruction Scheduling in the Saturn Vector Unit
Reference 5
- Resolution
- unresolved
- no resolver link, observed 2026-08-01T16:43:36.761133Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.