Pith. sign in

REVIEW 3 major objections 6 minor 34 references

Integrating programmable plasticity in experiment descriptions for analog neuromorphic hardware

T0 review · 3 major / 6 minor · reviewed 2026-08-11 · deepseek-v4-flash

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗ Review JSON

Pith's one-line read A unified PyNN description now expresses network topology, protocol, and programmable plasticity for the BrainScaleS-2 analog neuromorphic system, with kernels JIT-compiled onto embedded processors.

desk verdict A solid, well-scoped systems paper that integrates network, protocol, and plasticity descriptions for BSS-2; the main gap is that the scheduler's deadline-miss drops are silent and unevaluated. read the letter →

arxiv 2412.03128 v1 pith:JOCUNZRK submitted 2024-12-04 cs.NE

Philipp Spilger , Eric Müller , Johannes Schemmel This is my paper · ORCID
classification cs.NE
keywords BrainScaleS-2neuromorphichardwareplasticityspikingneuralnetworksPyNNcodegenerationonlinelearningembeddedprocessors
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper aims to close a gap in the BrainScaleS-2 software stack: previously, the network topology and experiment protocol were described separately from the plasticity algorithm, so implementing learning meant writing low-level code by hand. It introduces a unified, PyNN-based experiment description in which the user defines the spiking network, when plasticity rules should run, which observables to record, and the plasticity kernel itself in C++, all in one place. This enables users to exploit the full hybrid-plasticity arrangement of the hardware, with analog synapse circuits measuring correlations while digital embedded processors compute and apply updates, without manually placing rules onto hardware or scheduling them. The paper demonstrates the approach with a homeostatic firing-rate rule and reports that the embedded program is compiled in about 2.1 s and applies updates in as little as 2.28 µs per synapse.

What carries the argument

The central object is a `PlasticityRule` abstraction: a user-derived PyNN class that bundles the kernel function, a periodic or one-shot timing generator, and named observable recording specifications. The load-bearing mechanism is the pair of embedded SIMD processors on the chip, running a cross-compiled, code-generated program under an earliest-deadline-first scheduler; the scheduler fetches rule events during the experiment, executes kernels while the analog core evolves in continuous time, and skips any event whose deadline passes during another execution. The synapse circuits supply the expensive per-synapse correlation measurements directly, so the processor only evaluates the update rule and writes the result back, which is the hybrid-plasticity arrangement the platform was designed for.

What would settle it

Instrument the scheduler to count skipped events and run a multi-rule experiment whose kernels deliberately have worst-case execution times longer than their scheduling periods; if the log shows dropped invocations, the paper's correctness assumption is violated in that regime. A complementary check is to run a plasticity rule on 512 synapses and compare the recorded weight trajectory against a reference simulation to see whether deadline misses change the learned weights.

Watch

Extended reading notes

Core claim

The paper's central claim is that an integrated software path can connect the three previously separate descriptions of a neuromorphic experiment, namely network topology, experiment protocol, and plasticity algorithm, into one high-level PyNN description for BrainScaleS-2. In this design, a user-defined `PlasticityRule` class supplies a C++ kernel, a timing generator, and named observable recordings; the kernel is cross-compiled for the two embedded SIMD processors, and placement information from the hardware mapping is injected automatically at compile time. An earliest-deadline-first scheduler runs the rule kernels synchronously with the analog network's continuous-time evolution, letting them read synapse-local correlation and firing-rate observables, update weights or topology, and write recorded values to FPGA-attached DRAM that is read back and returned in PyNN data structures after the run. The authors demonstrate the path with a homeostatic rule that drives firing rates to a target value and report an execution-timing accuracy of about 10 µs.

Load-bearing premise

The framework assumes every plasticity kernel finishes before its next scheduled execution time, because the scheduler skips events whose deadline passes while another kernel is running; if a rule is too slow or too many rules compete, the missing update would silently corrupt the learning dynamics.

Editorial extensions

If this is right

  • Users can write multi-factor plasticity rules that touch both neurons and synapses at once, because one rule instance can be assigned to a population's cell type and a projection's synapse type together.
  • Several different plasticity rules can run in the same experiment, since the scheduler shares both embedded processors and lets each processor follow different code paths for its chip half.
  • Users never need to know final chip placement: the code-generation step embeds the mapped location of each accessible synapse and neuron directly into the compiled kernel.
  • Per-synapse and per-neuron observables chosen by the user are returned after the experiment in PyNN data structures, making the internal state of a plasticity rule visible to the modeler.
  • Compilation and code-generation time scale linearly with the number of rules, while per-synapse execution time for a SIMD-friendly rule improves as more target neurons are processed in parallel.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • An implication the paper leaves implicit is that the deadline-skipping scheduler makes plasticity correctness depend on worst-case kernel execution time, so the measured 2.28 µs per synapse for a simple homeostatic rule does not guarantee that complex multi-timescale rules will meet their deadlines.
  • The recording interface currently limits observables to packed or unpacked 8-bit and 16-bit integer values per synapse or neuron, which suggests the framework is best matched to rules with compact per-synapse state; rules needing rich per-event histories would have to encode that state manually.
  • Following the paper's own suggestion of connecting to an event-driven gradient-estimation front end, a plausible extension is a meta-learning loop in which plasticity-rule hyperparameters are treated as differentiable outer-loop parameters and the online plasticity rule as the inner loop, though no such experiment appears in the paper.
Share X Bluesky LinkedIn Reddit HN

Signed reviews

No signed human review yet.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 6 minor

Summary. The paper introduces a software framework for BrainScaleS-2 that unifies the description of spiking neural network experiments and programmable plasticity rules. Users specify network topology, experiment protocol, and a C++ "kernel" for each plasticity rule in a PyNN-based front end; the framework automatically generates code for the two embedded SIMD processors, schedules periodic rule invocations with an earliest-deadline-first scheduler, and records user-selected observables via FPGA-attached DRAM. The authors demonstrate the framework with a homeostatic plasticity rule that drives firing rates toward a 6 kHz target, reporting microsecond-level execution timing, sub-microsecond per-synapse update times for large populations, and specific compilation and code-generation times. The Discussion acknowledges several limitations, including finite processor speed, SIMD efficiency constraints, and the need to write low-level C++ code.

Significance. If the claims hold, this is a valuable integration contribution: it is the first PyNN-level description that covers network topology, experiment timing, and programmable plasticity together for BrainScaleS-2, with JIT compilation, automatic placement annotation, and a user-extensible observable-recording path. The paper's strengths are that it builds on a real hardware platform, reports measured timing values (10(3) µs execution-timing accuracy, best 2.28(6) µs per plastic synapse), gives concrete algebraic scaling estimates in Eqs. (2) and (3), and makes the demonstration publicly available through the EBRAINS infrastructure. The presented rule uses no fitted parameters and the measured convergence is a genuine functional check. However, the central correctness gap identified in Section III-A and Figure 2—silent dropping of plasticity events whose deadlines are missed—means the framework's promised semantics are not yet fully established, and the single-rule evaluation in Section III-E does not exercise that gap.

major comments (3)
  1. [Section III-A, Figure 2] The earliest-deadline-first scheduler skips plasticity events whose deadlines pass during another rule's execution, and this skip is silent: the manuscript provides no mechanism to count, report, log, or otherwise make the user aware that an invocation was dropped. Because the framework's central claim is that user-specified rule execution timing is preserved, an undetected skip means the experiment can deviate from the specification without leaving any trace in the recorded observables. This is not merely a performance limitation: for timing-sensitive rules such as STDP or reward-modulated plasticity, a single dropped update can change the learning trajectory. Please add a skip counter or flag exposed to the host, an option to fail or warn when a deadline is missed, and a demonstration that this behavior is observable.
  2. [Section III-E, Eq. (1), Figure 4] The evaluation exercises only one simple homeostatic rule with a unit sign update. The paper does not state the scheduled rule period, does not report whether any deadline misses occurred, and does not compare the measured weight/firing-rate trajectories against a numerical baseline. The claimed "timing accuracy of 10(3) µs" is therefore only established for the least demanding case. Please evaluate with multiple concurrent rules, rules whose kernels have variable or deliberately worst-case durations, and scheduling periods close to the kernel execution time; report the number of missed deadlines and compare the learned trajectories to a reference implementation to quantify the correctness impact.
  3. [Section III-A, Section IV] The Discussion states that "the continuous-time dynamics of the analog core and the finite processor speed limit the complexity of plasticity rules with strict temporal requirements," but this frames the issue as a performance ceiling rather than a correctness hazard. The manuscript's execution model has no guarantee that a kernel finishes before its next deadline, and a skipped event is not distinguishable from an event that never existed. The paper should either provide such a guarantee (e.g., by offline schedulability analysis based on measured kernel durations) or explicitly define the semantics of missed deadlines and state which classes of plasticity rules are safe under those semantics.
minor comments (6)
  1. [Abstract, Section I] The hardware name is inconsistently split as "Brain ScaleS-2" in several places (e.g., the abstract and "The Brain ScaleS-2 neuromorphic architecture"); it should be "BrainScaleS-2" throughout.
  2. [Figure 4E] The horizontal axis label uses "dt [us]" while the text uses "µs"; please use a single unit notation throughout.
  3. [Section III-C, Listings 1-3] The timing generator is described as supporting periodic and one-shot execution, but no code example is given. Include a concrete snippet showing how a user specifies the period and phase for a rule, and how multiple rules' schedules interact with the scheduler.
  4. [Eqs. (2) and (3)] The symbols #columns, #rows, and #neurons are used without formal definitions; please define them as the number of synapse columns, synapse rows, and neuron circuits for the relevant projection or population.
  5. [References] References [23] and [28] cite the same PyNN paper; consolidate to a single reference.
  6. [Section III-A, Figure 2 caption] The caption relies on color to distinguish different plasticity rules; since the figure may be viewed in grayscale, add textual labels to the schedule bars or describe the patterns used.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the framework is an engineering contribution whose evaluation is a functional check, not a prediction derived from fitted inputs or self-citations.

full rationale

The paper introduces a unified PyNN-based framework for describing experiments and programmable plasticity on BrainScaleS-2, together with a scheduler, code generation, and an evaluation using a homeostatic plasticity rule. No load-bearing step reduces to its own inputs by construction. The plasticity update in Eq. 1 is a user-supplied learning rule, and the observed convergence to the target firing rate is a functional demonstration of the hardware/software integration, not a prediction fitted from or defined by the framework's outputs. The scaling formulas in Eqs. 2 and 3 are algebraic memory-footprint estimates, not fitted quantities. Citations to prior BSS-2 software components (e.g., [22], [26], [29]) are normal engineering dependencies and are not invoked as an external proof of the central contribution; no uniqueness theorem or ansatz is imported from the authors' prior work. The scheduler's behavior of skipping events whose deadlines pass during another execution is a correctness limitation acknowledged in the Discussion, but that is a performance/correctness concern, not circular reasoning. The central claim remains independently supported by the demonstrated end-to-end experiment, and the skeleton of the evaluation is reproducible via the EBRAINS demo link.

Assumptions & free parameters 0 free parameters · 4 assumptions · 0 invented entities

No fitted parameters or invented entities appear. The contribution is software integration, so the ledger records the domain assumptions about the BSS-2 hardware and toolchain that the framework rests on.

assumptions (4)
  • domain assumption BSS-2 hardware operates as described: 512 analog AdEx neurons, 256 synapses each, and two embedded SIMD Power processors with access to observables.
    Invoked throughout Methods; the framework's behavior depends on these hardware capabilities and on the analog emulation being sufficiently accurate for the demonstrated rule.
  • domain assumption The custom software toolchain (gcc extended for BSS-2, newlib, hardware abstraction layer) compiles the user C++ kernels correctly for the embedded processors.
    The JIT compilation and code generation pipeline in Section III-D assumes cross-compilation and memory layout are correct.
  • domain assumption PyNN semantics and the graph-based backend correctly represent network topology and map it to hardware.
    Section III-C relies on PyNN populations and projections and on placement mapping from the previous stack [22].
  • domain assumption Observed firing rates, extracted by binning recorded spikes, accurately reflect neuron activity during the experiment.
    The evaluation in Section III-E uses binned spike trains (50 ms bins) to assert convergence to the target rate; no ground-truth comparison is provided.

how reviews work

0 comments
Cite this review

Pith. "Pith review of Integrating programmable plasticity in experiment descriptions for analog neuromorphic hardware." pith.science (2026). https://pith.science/paper/JOCUNZRK

@misc{pith2026241203128,
  author       = {Pith},
  title        = {Pith review of: Integrating programmable plasticity in experiment descriptions for analog neuromorphic hardware},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/JOCUNZRK}},
  note         = {Machine review of arXiv:2412.03128}
}
read the original abstract

The study of plasticity in spiking neural networks is an active area of research. However, simulations that involve complex plasticity rules, dense connectivity/high synapse counts, complex neuron morphologies, or extended simulation times can be computationally demanding. The BrainScaleS-2 neuromorphic architecture has been designed to address this challenge by supporting "hybrid" plasticity, which combines the concepts of programmability and inherently parallel emulation. In particular, observables that are expensive in numerical simulation, such as per-synapse correlation measurements, are implemented directly in the synapse circuits. The evaluation of the observables, the decision to perform an update, and the magnitude of an update, are all conducted in a conventional program that runs simultaneously with the analog neural network. Consequently, these systems can offer a scalable and flexible solution in such cases. While previous work on the platform has already reported on the use of different kinds of plasticity, the descriptions for the spiking neural network experiment topology and protocol, and the plasticity algorithm have not been connected. In this work, we introduce an integrated framework for describing spiking neural network experiments and plasticity rules in a unified high-level experiment description language for the BrainScaleS-2 platform and demonstrate its use.

Figures

Figures reproduced from arXiv: 2412.03128 by the authors.

Figure 1
Figure 1. A photo of the BSS-2 chip with its schematic on top. One embedded SIMD processor per chip half accesses on-chip observables, such as synapse￾local pre-/post-timed spike correlation information, mean neuronal activities, or firing rates, and modifies neuron and synapse parameterization (e.g., weights), and topology (e.g., to implement structural plasticity) defined by a plasticity algorithm. processors can directly a… view at source ↗
Figure 2
Figure 2. Scheduling of plasticity rules on the embedded processors. Different [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. visualizes the implemented execution model in￾cluding plasticity: this work implemented the red components. B. Data flow Experiments on neuromorphic hardware often require access to observables during or after execution. In addition to spikes, neuronal or synaptic dynamics, in experiments with plasticity the evolution of the configuration of altered network components is of interest. During experiment design, plasti… view at source ↗
Figures from the paper (1 more)
Figure 4
Figure 4. Figure 4: Evaluation of an exemplary homeostatic plasticity rule. A Poisson source of [PITH_FULL_IMAGE:figures/full_fig_p006_4.png]

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

34 extracted references · 16 canonical work pages

  1. [1]

    Extremely scalable spiking neuronal network simulation code: From laptops to exascale computers,

    J. Jordan et al., “Extremely scalable spiking neuronal network simulation code: From laptops to exascale computers,” Frontiers in Neuroinformatics, vol. 12, p. 2,

    work page

  2. [2]

    Overview of the SpiNNaker system architecture,

    S. B. Furber et al., “Overview of the SpiNNaker system architecture,” IEEE Transactions on Computers , vol. 62, no. 12, 2013. DOI: 10.1109/TC.2012.142

    work page doi:10.1109/tc.2012.142 2013

  3. [3]

    Spynnaker: A software package for running pynn simulations on spinnaker,

    O. Rhodes et al., “Spynnaker: A software package for running pynn simulations on spinnaker,” Frontiers in Neuroscience, vol. 12, p. 816, 2018. DOI: 10.3389/fnins. 2018.00816

    arXiv 2018

  4. [4]

    Efficient neuromorphic signal pro- cessing with Loihi 2,

    G. Orchard et al., “Efficient neuromorphic signal pro- cessing with Loihi 2,” in 2021 IEEE Workshop on Signal Processing Systems (SiPS) , IEEE, 2021, pp. 254–259. DOI: 10.1109/SiPS52927.2021.00053

    arXiv 2021

  5. [5]

    Large-scale neuromorphic spiking array processors: A quest to mimic the brain,

    C. S. Thakur et al., “Large-scale neuromorphic spiking array processors: A quest to mimic the brain,” Front. Neurosci., vol. 12, p. 891, 2018. DOI: 10.3389/fnins. 2018.00891

    arXiv 2018

  6. [6]

    NEST (NEural Simulation Tool),

    M.-O. Gewaltig et al., “NEST (NEural Simulation Tool),” Scholarpedia, vol. 2, no. 4, p. 1430, 2007. DOI: 10.4249/ scholarpedia.1430

    work page 2007

  7. [7]

    Brian 2, an intuitive and efficient neural simulator,

    M. Stimberg et al., “Brian 2, an intuitive and efficient neural simulator,” eLife, vol. 8, Aug. 2019. DOI: 10. 7554/eLife.47314

    work page 2019

  8. [8]

    The impact of studying brain plasticity,

    P. Mateos-Aparicio et al., “The impact of studying brain plasticity,” Front. Cell. Neurosci., vol. 13, 2019. DOI: 10.3389/fncel.2019.00066

    arXiv 2019

Show all 34 references
  1. [9]

    Models of metaplasticity: A review of concepts,

    P. Yger et al., “Models of metaplasticity: A review of concepts,” Front. Comp. Neurosci., vol. 9, p. 138, 2015. DOI: 10.3389/fncom.2015.00138

    2015

  2. [10]

    Memory consolidation and im- provement by synaptic tagging and capture in recurrent neural networks,

    J. Luboeinski et al. , “Memory consolidation and im- provement by synaptic tagging and capture in recurrent neural networks,” Commun. Biol., vol. 4, no. 1, pp. 1–17, Mar. 2021. DOI: 10.1038/s42003-021-01778-y

    2021 doi

  3. [11]

    Evolving interpretable plasticity for spiking networks,

    J. Jordan et al. , “Evolving interpretable plasticity for spiking networks,” eLife, vol. 10, M. C. W. van Rossum et al. , Eds., e66273, Oct. 2021. DOI: 10.7554/eLife. 66273

    2021 doi

  4. [12]

    Neuromorphic hardware learns to learn,

    T. Bohnstingl et al. , “Neuromorphic hardware learns to learn,” Frontiers in Neuroscience, vol. 2019, no. 13, pp. 1–14, May 2019. DOI: 10.3389/fnins.2019.00483

    2019

  5. [13]

    Code generation in computational neuroscience: A review of tools and techniques,

    I. Blundell et al. , “Code generation in computational neuroscience: A review of tools and techniques,” Fron- tiers in Neuroinformatics , vol. 12, p. 68, 2018. DOI: 10.3389/fninf.2018.00068

    2018

  6. [14]

    GeNN: A code generation framework for accelerated brain simulations,

    E. Yavuz et al., “GeNN: A code generation framework for accelerated brain simulations,” Scientific reports , vol. 6, no. 1, pp. 1–14, 2016

    2016

  7. [15]

    Sabne, XLA: Compiling machine learning for peak performance, 2020

    A. Sabne, XLA: Compiling machine learning for peak performance, 2020

    2020

  8. [16]

    Frameworks for SNNs: A review of data science-oriented software and an expansion of SpykeTorch,

    D. L. Manna et al., “Frameworks for SNNs: A review of data science-oriented software and an expansion of SpykeTorch,” in Engineering Applications of Neural Networks, L. Iliadis et al., Eds., Cham: Springer Nature Switzerland, 2023, pp. 227–238. DOI: 10.1007/978-3- 031-34204-2_20

    2023 doi

  9. [17]

    Structural plasticity on an accel- erated analog neuromorphic hardware system,

    S. Billaudelle et al., “Structural plasticity on an accel- erated analog neuromorphic hardware system,” Neural networks: the official journal of the International Neural Network Society, vol. 133, pp. 11–20, Jan. 2021. DOI: 10.1016/j.neunet.2020.09.024

    2021 doi

  10. [18]

    Versatile emulation of spiking neu- ral networks on an accelerated neuromorphic substrate,

    S. Billaudelle et al., “Versatile emulation of spiking neu- ral networks on an accelerated neuromorphic substrate,” in 2020 IEEE International Symposium on Circuits and Systems (ISCAS) , IEEE, Oct. 2020. DOI: 10.1109/ iscas45731.2020.9180741

    2020

  11. [19]

    Control of criticality and computation in spiking neuromorphic networks with plasticity,

    B. Cramer et al., “Control of criticality and computation in spiking neuromorphic networks with plasticity,” Na- ture communications, vol. 11, p. 2853, Jun. 2020. DOI: 10.1038/s41467-020-16548-3

    2020 doi

  12. [20]

    Autocorrelations from emergent bistability in homeostatic spiking neural networks on neu- romorphic hardware,

    B. Cramer et al. , “Autocorrelations from emergent bistability in homeostatic spiking neural networks on neu- romorphic hardware,” Phys. Rev. Research, vol. 5, no. 3, p. 033 035, Jul. 2023. DOI: 10.1103/PhysRevResearch.5. 033035

    2023 doi

  13. [21]

    Demonstrating advantages of neuromorphic computation: A pilot study,

    T. Wunderlich et al. , “Demonstrating advantages of neuromorphic computation: A pilot study,” Frontiers in Neuroscience, vol. 13, p. 260, 2019. DOI: 10.3389/ fnins.2019.00260

    2019

  14. [22]

    A scalable approach to modeling on accelerated neuromorphic hardware,

    E. Müller et al., “A scalable approach to modeling on accelerated neuromorphic hardware,” Front. Neurosci., vol. 16, 2022. DOI: 10.3389/fnins.2022.884128

    2022

  15. [24]

    The BrainScaleS-2 accelerated neuro- morphic system with hybrid plasticity,

    C. Pehle et al., “The BrainScaleS-2 accelerated neuro- morphic system with hybrid plasticity,” Front. Neurosci., vol. 16, 2022. DOI: 10.3389/fnins.2022.795876

    2022

  16. [25]

    PowerISA version 2.06 revision b,

    PowerISA, “PowerISA version 2.06 revision b,” Power.org, Specification, Jul. 2010

    2010

  17. [26]

    Demonstrating hybrid learning in a flexible neuromorphic hardware system,

    S. Friedmann et al., “Demonstrating hybrid learning in a flexible neuromorphic hardware system,” IEEE Trans- actions on Biomedical Circuits and Systems , vol. 11, no. 1, pp. 128–142, Feb. 2017. DOI: 10.1109/TBCAS. 2016.2579164

    2017

  18. [27]

    Friedmann, Omnibus on-chip bus , forked from https: //github.com/five-elephants/omnibus, 2015

    S. Friedmann, Omnibus on-chip bus , forked from https: //github.com/five-elephants/omnibus, 2015

    2015

  19. [28]

    PyNN: A common interface for neuronal network simulators,

    A. P. Davison et al. , “PyNN: A common interface for neuronal network simulators,” Front. Neuroinform., vol. 2, no. 11, 2009. DOI: 10.3389/neuro.11.011.2008

    2009 doi

  20. [29]

    Extending BrainScaleS OS for BrainScaleS-2,

    E. Müller et al. , “Extending BrainScaleS OS for BrainScaleS-2,” Electronic Vision(s), Kirchhoff Institute for Physics, Heidelberg University, Germany, Heidelberg, Germany, Tech. Rep., Mar. 2020. DOI: 10.48550/arXiv. 2003.13750

    2020 doi arXiv

  21. [30]

    Vinkelis, Bitsery, https://github.com/fraillt/bitsery, 2020

    M. Vinkelis, Bitsery, https://github.com/fraillt/bitsery, 2020

    2020

  22. [31]

    Dietrich et al., Multi-compartment models with STDP on BrainScaleS-2, 2023

    R. Dietrich et al., Multi-compartment models with STDP on BrainScaleS-2, 2023. DOI: 10.12751/NNCN.BC2023. 112

    2023 doi

  23. [32]

    Atoui et al., Multi-timescale synaptic plasticity on analog neuromorphic hardware , 2024

    A. Atoui et al., Multi-timescale synaptic plasticity on analog neuromorphic hardware , 2024. arXiv: 2412 . 02515 [q-bio.QM]

    2024

  24. [33]

    LEMS: A language for expressing complex biological models in concise and hierarchical form and its use in underpinning NeuroML 2,

    R. C. Cannon et al., “LEMS: A language for expressing complex biological models in concise and hierarchical form and its use in underpinning NeuroML 2,” Front. Neuroinform., vol. 8, p. 79, 2014. DOI: 10.3389/fninf. 2014.00079

    2014

  25. [34]

    Jaxsnn: Event-driven gradient esti- mation for analog neuromorphic hardware,

    E. Müller et al. , “Jaxsnn: Event-driven gradient esti- mation for analog neuromorphic hardware,” in Neuro- inspired Computational Elements Workshop (NICE 2024), 2024. DOI: 10.1109/NICE61972.2024.10548709

    2024

  26. [2018]

    DOI: 10.3389/fninf.2018.00002

    2018

Pith tools

Reviewed August 11, 2026 · model on record in the stance chip above.