Pith. sign in

REVIEW 3 major objections 4 minor 59 references

Toward an Ion-Based Large-Scale Integrated Circuit: Circuit Level Design, Simulation, and Integration of Iontronic Components

T0 review · 3 major / 4 minor · reviewed 2026-08-12 · deepseek-v4-flash

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗ Review JSON

Pith's one-line read A five-parameter equivalent-circuit model lets iontronic diode logic gates be simulated in standard chip-design tools and predicts measured five-gate cascades within 3σ.

desk verdict A genuine first SPICE-style compact model for iontronic circuits, with honest static validation, but the acknowledged failure to model the 1V-to--1V transient undercuts the dynamic circuit claims. read the letter →

arxiv 2412.07784 v1 pith:KPZVH4ET submitted 2024-11-25 cs.ET

Noa Edri Fraiman , Barak Sabbagh , Gilad Yossifon , Alexander Fish This is my paper · ORCID
classification cs.ET
keywords iontronicscompactmodelnanofluidicdiodecircuitsimulationVerilog-AMonteCarloanalysisiontroniclogicgatesintegratedcircuits
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper aims to establish that iontronics can be given the design-tool layer microelectronics has relied on since the 1960s: a compact circuit model that lets a designer simulate many iontronic components together before fabrication. It proposes a five-parameter equivalent circuit for the iontronic bipolar diode—a voltage-dependent resistor and capacitor in parallel, in series with a parasitic resistance—calibrated from current-voltage curves and step-response measurements. Implemented in Verilog-A and run in a standard commercial circuit simulator, the model reproduces the measured behavior of single diodes, AND and OR gates, and a five-gate OR cascade, with cascade outputs within three standard deviations of experiment. Because each Monte Carlo trial is cheap, the model also becomes a tool for studying chip-to-chip fabrication variability and for exploring design trade-offs such as cascadability, decoder margins, and frequency response. If the claim is right, iontronic circuits can be designed and yield-predicted in the same workflow as electronic chips, and the modeling route can be extended to other iontronic components.

What carries the argument

The load-bearing object is the iontronic diode equivalent circuit: $R_e$ in series with the parallel pair $R_p(V)$ and $C_p(V)$, where $R_p$ and $C_p$ each take one of two constant values depending on whether the internal node voltage $V_c$ is negative or nonnegative. The dynamic behavior is carried by the single-exponential relaxation time $\tau = C_p R_p R_e/(R_p+R_e)$, which links the measured current decay to the capacitance values and makes the circuit simulable. A Monte Carlo statistical add-on samples $R_p^+$ and $R_p^-$ from log-normal distributions fitted to measured on/off currents, turning the compact model into a yield-analysis tool. The paper notes that this simplified model misses the forward-to-reverse transition, where the measured transient is not exponential and a fractional (memory) element would be needed.

What would settle it

Measure the current response of a single diode to a 1 V to $-1$ V step and fit it with the model's exponential decay formula: the paper already reports that the fit fails. A stronger test is to measure the high-to-low output transient of a cascaded OR gate and compare its settling time with the model's prediction; if the discharge tail is systematically slower or multi-timescale, the dynamic claim collapses.

Watch

Extended reading notes

Core claim

The central discovery is that the nonlinear steady-state and switching behavior of a polyelectrolyte bipolar ion diode can be captured by a compact two-state RC equivalent circuit with only five parameters: a constant series resistance $R_e$, forward and reverse resistors $R_p^+$ and $R_p^-$, and two capacitors $C_p^+$ and $C_p^-$. Calibration uses the measured I-V slope in each bias region, the overshoot current at the moment of switching, and two single-exponential time constants extracted from step responses. The model is written in Verilog-A and run in the Spectre circuit simulator, and when process variations are added through Monte Carlo sampling, the simulated outputs of a five-gate OR cascade agree with measurements within three standard deviations. The paper then uses the model predictively: it maps maximum cascade length against rectification ratio and device uniformity, simulates a 24-gate dual-rail 3-to-8 decoder, and shows that reducing diode capacitance by a factor of 1000 would raise the maximum operating frequency from about 0.1 mHz to 0.1 Hz for a diode-bridge rectifier.

Load-bearing premise

The model assumes every transient is a single exponential with one of two fixed capacitance values; the measured jump from 1 V to $-1$ V is not exponential, so the settling-time and frequency predictions depend on a premise that at least one measured scenario already violates.

Editorial extensions

If this is right

  • Iontronic logic can be designed and debugged in a commercial VLSI flow before any fabrication, which is not currently possible for multi-gate iontronic chips.
  • Cascadability improves with both higher rectification ratio and tighter device uniformity; with a tenfold smaller parameter spread, a 15-gate chain needs a rectification ratio near 25 instead of 100.
  • Dual-rail logic removes the inverter bottleneck, enabling a 24-gate iontronic 3-to-8 decoder whose high-to-low margin, settling time, and power can be traded against $R_p^-$.
  • A 1000-fold reduction in diode capacitance shifts the maximum operating frequency from about 0.1 mHz to 0.1 Hz, bringing diode-bridge AC-to-DC conversion closer to practical use.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Editorial inference: if the two-state RC template proves portable, other iontronic components—transistors, memristors, capacitors—could receive first-order compact models in the same way, allowing hybrid electronic-iontronic systems to be simulated before physics-based models exist.
  • Editorial inference: the failure of the single-exponential assumption on the 1 V to $-1$ V transition suggests a fractional capacitor or internal state variable is the next required add-on; adding it could change settling-time and frequency predictions in diode-based logic, where outputs discharge through reverse-biased diodes.
  • Editorial inference: the 500 mV output and 99% yield cascade criterion could serve as a noise-margin-like figure of merit for comparing future iontronic device technologies.
  • Editorial inference: the predicted frequency scaling sets a concrete device target: $C_p$ must fall by many orders of magnitude to reach even audio-range operation, which points to junction geometry and permselectivity as the knobs to turn.
Share X Bluesky LinkedIn Reddit HN

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 4 minor

Summary. The paper proposes a compact model for an iontronic bipolar diode, comprising a voltage-dependent resistor and capacitor in parallel with a series parasitic resistance, and implements it in Verilog-A within the Cadence Spectre environment. The five model parameters are calibrated from I-V characteristics and step-response time constants, and Monte Carlo simulations are used to capture diode-to-diode variability. The model is then used to simulate AND/OR gates, a five-OR-gate cascade, cascadability limits, a dual-rail decoder, and a diode-bridge rectifier, with comparisons to measurements from the authors' prior work reported as falling within 3σ. The paper argues that this establishes a circuit-level design and simulation methodology for iontronic integrated circuits.

Significance. If the predictive claims hold, this would be an important step: it would give iontronic circuit designers a compact-model simulation capability analogous to electronic circuit simulation, enabling pre-fabrication design, statistical analysis, and exploration of design trade-offs. The model is exactly identified (five parameters, five constraints), and the Monte Carlo treatment of device variability is a genuine methodological contribution. The static I-V and gate-level validations provide some grounding for steady-state predictions. However, the dynamic predictive claim is substantially weakened by an acknowledged unmodeled memory effect for the forward-to-reverse voltage transition, which is a common high-to-low logic transition in diode-based circuits. Because the dynamic behavior is central to several results (settling time, frequency response, cascading), the significance of the work as presented is conditional on resolving or carefully bounding this limitation.

major comments (3)
  1. [Results, Phase II; Methods, Eqs. [6]-[14]] The compact model assumes single-exponential relaxation with constant capacitance values Cp+ and Cp-, and the calibration uses Eqs. [12] and [13] to fix those capacitances. For the 1 V to -1 V transition, the paper states that the measured time constant is about 46 s, while Eq. [14] predicts tau(1,-1) = Cp+ Re (approximately 205 s using the reported values), and the paper explicitly acknowledges that "to capture this experimental feature, more complexity needed to be added to the model." The 1 V to -1 V transition is not a peripheral case: in diode-based logic it is precisely the transition an output undergoes when discharging from logic-high to logic-low. Therefore the dynamic simulations in Fig. 4(b) (cascaded OR gates), Fig. 5(c) (decoder settling time), and Fig. 5(e) (diode bridge transient) all rely on a model that is known to be invalid for that operating condition. The static I-V agreement and the 0-to-1 V step-response agreement do not test this assumption. The claim that the model predicts iontronic circuit dynamics within 3σ is therefore not established for a load-bearing condition, and the manuscript needs either to extend the model to capture the memory effect or to restrict and re-state the predictive claims accordingly.
  2. [Figure 4(b) and associated text] The five-OR-gate cascade validation is presented as evidence that the model predicts complex circuit behavior within 3σ, but the paper does not specify whether the measurement and simulation waveforms contain forward-to-reverse transitions of the kind identified above. If the cascade outputs are only exercised under conditions that avoid the problematic 1 V to -1 V step, the validation does not cover the model's known failure mode. The authors should report the input stimulus and the voltage trajectories of the intermediate and final gate outputs, and should either demonstrate that the problematic transition is negligible in this circuit or exclude dynamic claims for circuits that contain it.
  3. [Results, 'Circuit simulation with iontronic diodes' and Figure 5] The decoder settling time (Fig. 5(c)) and the diode-bridge frequency response (Fig. 5(e)) are presented as quantitative design insights, yet both quantities depend on the dynamic behavior around high-to-low transitions. Since the model's dynamic response for forward-to-reverse bias is explicitly unmodeled, these simulation results should be labeled as qualitative exploratory projections rather than as validated predictions. The paper currently does not provide a sensitivity analysis showing how the unmodeled memory effect would affect these results.
minor comments (4)
  1. [Throughout] There are several typographical errors, including "remined" (Figure 2 caption), "volage" (Results, Phase II), "contructing" (Results, Model of process variation), and an unresolved placeholder "Error! Reference source not found." in the Methods section.
  2. [Methods, equations] The Methods section restarts equation numbering at [1], creating confusion with the equation numbers used in the Results section; the text should use a consistent numbering scheme across the manuscript.
  3. [Figure M1] The Methods text refers to "Figure M1" but the figure is neither labeled with that number nor mentioned in the main text; the reference should be corrected or the figure should be properly integrated.
  4. [References] Reference [44] is cited in the sentence "In [44] A possible implementation ..." in an awkward and grammatically incomplete way; the citation should be integrated into a complete sentence.

Circularity Check

2 steps flagged · score 4.0 of 10

Dynamic 'validation' is in-sample: the step-response transients used to calibrate Cp± are re-presented as 'predictions,' and the Monte Carlo 3σ agreement is checked against the same batch whose resistance distributions were fitted; static circuit predictions, however, are computed, not fit.

  1. fitted input called prediction [Results, Phase II: Calibration, Fig. 3(a); Methods, Eqs. [12]–[16]]
    "After calibrating the parameters, we implemented the model in MATLAB to examine its suitability to assess the full dynamic electric behavior of the iontronic diode in various step voltage scenarios (Figure 3(a)). As expected, the model predicted all scenarios well, except for a single case involving the transition from forward to reverse bias."

    The simulated transients in Fig. 3(a) for the 0→1 V and 0→-1 V steps are not out-of-sample predictions: the time constants of those very transients, τ_{0,1}=71 s (Eq. [12]) and τ_{0,-1}=0.54 s (Eq. [13]), were the two calibration constraints used to solve for Cp+ and Cp- (Eqs. [15]–[16]). The single-exponential waveforms the model 'predicted' carry exactly the fitted time constants, so the agreement is the calibration fit re-plotted.

  2. fitted input called prediction [Results, 'Model of process variation effects as the first add-on to the core model' and Fig. 4(b)]
    "Consequently, the statistical distributions of 𝑅௣ା and 𝑅௣ି were derived from the measured steady-state currents (Ion and Ioff) across 15 diodes... the experimental results were within three standard deviations (3σ) of the simulated data, indicating good agreement between the observed and predicted values."

    The Monte Carlo input distributions are fitted to the same chip whose five-OR-gate outputs are then declared 'predicted... within 3σ' (measurements taken from the authors' own prior work [28] on the same batch). The simulated output distribution is the deterministic image of the fitted resistance distributions through the circuit topology, so the agreement is partly in-sample: it confirms that the model maps device statistics to circuit statistics, but it is not an out-of-sample prediction. It is not forced by construction (a wrong topology or wrong Re would still miss), so the static circuit claim retains independent content, but the 'predicted' wording overstates the strength of the validation.

full rationale

The central derivation is not circular: the five model parameters (Re, Rp-, Rp+, Cp-, Cp+) are calibrated solely from single-diode quasi-steady I-V data and step-response transients (Methods Eqs. [1]–[16]), and the AND/OR gate, cascaded OR, decoder, and diode-bridge outputs are computed by simulating the fitted device model — no circuit-level output feeds back into the fit. The static gate and cascade agreement against measurements from the authors' own prior fabrication [28] is genuine evidence for the equivalent-circuit topology, even though [28] largely shares the present authors and the same batch. Two in-sample elements weaken the 'prediction' language: (i) the single-diode transients used to calibrate Cp± are re-presented as 'predicted' (Fig. 3(a)), and the one uncalibrated transition (1 V to -1 V) is the only one the model fails; (ii) the Monte Carlo parameter distributions and the 3σ-validated cascade outputs come from the same fabrication batch. The authors disclose the dynamic-model limitation explicitly ('to capture this experimental feature, more complexity needed to be added to the model') and attribute it to a memory effect; this is a disclosed correctness limitation that propagates into dynamic circuit predictions (settling time, maximum frequency, decoder behavior) but is not hidden circularity. Overall: partial, mild circularity — some fitted inputs are relabeled as predictions, while the central circuit-prediction claim still has independent content that is not forced by construction.

Assumptions & free parameters 6 free parameters · 5 assumptions · 0 invented entities

The model is a behavioral fit: five free parameters are calibrated from two independent measurements (I-V and step response). No new physical entities are introduced; the fractional capacitor is noted as needed for future versions but not implemented.

free parameters (6)
  • Re = 5.5e5 Ω
    Series resistance of interconnecting microchannels, extracted from the peak overshoot current when the diode is switched from 0 V to 1 V (Methods, Eq. [3]).
  • Rp+ = 2.9e5 Ω
    Forward-bias steady-state resistance of the diode junction, obtained from the total steady-state resistance (8.4e5 Ω) minus Re (Methods, Eq. [4]).
  • Rp- = 4.84e9 Ω
    Reverse-bias steady-state resistance of the diode junction, obtained from the total steady-state resistance (4.9e9 Ω) minus Re (Methods, Eq. [5]).
  • Cp+ = 3.74e-4 F
    Capacitance in forward bias, computed from the step-response time constant for 0 to 1 V (tau = 71 s) using Eq. [12].
  • Cp- = 9.93e-9 F
    Capacitance in reverse bias, computed from the step-response time constant for 0 to -1 V (tau = 0.54 s) using Eq. [13].
  • Lognormal parameters for Rp+ and Rp- (mean, std) = Not reported numerically
    The statistical distributions used in Monte Carlo simulation are fitted to measured steady-state currents (Ion, Ioff) of multiple diodes on the chip (Results, Phase II); the distribution parameters are not given in the paper.
assumptions (5)
  • domain assumption The diode's steady-state current-voltage characteristic can be represented as piecewise linear with two constant resistances Rp+ (forward) and Rp- (reverse) separated at Vc=0.
    Used to write constraints [1] and [2] in Methods; Figure 2(e) shows resistance varies within each bias region, so this is an approximation.
  • domain assumption The transient response follows a single exponential time constant described by a first-order linear ODE (Eq. [6]) with constant capacitance Cp in each bias region.
    Used to derive the current relaxation expressions (Eqs. [7]-[11]) and to calibrate Cp+ and Cp-; the paper itself reports that the 1 V to -1 V transition violates this assumption (memory effect, Ref. [40]).
  • domain assumption The microchannel resistance Re is constant and identical for all diodes, while only Rp+ and Rp- vary between diodes.
    Assumed in the Monte Carlo variation model (Results, Phase II); variations in junction dimensions are attributed only to Rp.
  • standard math Standard calculus: solution of dQ/dt + kQ = constant is Q = constant + A exp(-t/tau).
    Used throughout Methods, Eqs. [6]-[10].
  • ad hoc to paper The memory effect invoked to explain the 1 V to -1 V mismatch is not part of the compact model.
    The paper speculates that the discrepancy is related to a memory effect but does not model it, leaving the model's dynamic accuracy limited (Results, Phase II).

how reviews work

0 comments
Cite this review

Pith. "Pith review of Toward an Ion-Based Large-Scale Integrated Circuit: Circuit Level Design, Simulation, and Integration of Iontronic Components." pith.science (2026). https://pith.science/paper/KPZVH4ET

@misc{pith2026241207784,
  author       = {Pith},
  title        = {Pith review of: Toward an Ion-Based Large-Scale Integrated Circuit: Circuit Level Design, Simulation, and Integration of Iontronic Components},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/KPZVH4ET}},
  note         = {Machine review of arXiv:2412.07784}
}
read the original abstract

Iontronics combines ions as charge carriers with electronic-like operations, enabling unique information processing, chemical regulation, and enhanced bio-integrability. Standard simulation tools encounter difficulties in effectively modeling the behavior of integrated iontronic components, highlighting the need for specialized design and simulation approaches. This paper presents a design methodology for iontronic integrated circuits, inspired by well-established electronic design methodologies and made possible by the development of a compact model for the iontronic bipolar diode. Grounded in the diode's physical properties and observed behavior, this model provides a conceptual framework that could be applied to other iontronic components. It is implemented using standard VLSI (Very Large-Scale Integration) electronic design tools, enabling simulations that demonstrate diode-based iontronic circuit behaviors and laying the groundwork for the design and simulation of hybrid systems integrating electronic and iontronic circuits. The proposed iontronic circuit simulation approach enables the exploration of how component uniformity influences circuit behavior, as well as the impact of diode parameters and a deeper understanding of diode characteristics from a circuit perspective. These insights are expected to contribute to the development of more complex and efficient iontronic circuits, bringing us closer to practical and groundbreaking applications in the field.

Figures

Figures reproduced from arXiv: 2412.07784 by the authors.

Figure 1
Figure 1. (a) Abstraction Levels in the Integrated Circuit Design Process. The bottom section of the diagram shows the conventional abstraction levels in electronic design, that move from the device level, circuit design, logic design, and system- level design. The top section suggests how to apply similar abstraction levels to iontronic systems. A and B are the inputs, Y and Q are the outputs, and Vdd and Vss are the positiv… view at source ↗
Figure 3
Figure 3. (a) Step-response measurement and simulation: The behavior of the iontronic diode’s current (𝐼஽௜௢ௗ௘) as a function of time for 4 different transitions of the input voltage (𝑉஽௜௢ௗ௘ = 0, −1,1 𝑉). The red line represents the experimental results, and the blues lines represent the simulation results using two different tools – Matlab and Spectre. (b) An image of 9 fabricated diodes: the variation in the physical paramet… view at source ↗
Figure 4
Figure 4. (a) Logic Gate Simulation and Measurement: Measurements (taken from Sabbagh et al. [28]) and 5-point Monte Carlo simulations of AND and OR gates using the iontronic compact model. (b) Cascaded OR Gates: A 200-point Monte Carlo simulation of five cascaded OR gates, where each simulation point produced a different circuit output due to statistical variations. The resulting output voltages for each gate in the chain ar… view at source ↗

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

59 extracted references · 59 canonical work pages

  1. [12]

    Integrated Photonic Computing beyond the von Neumann Architecture,

    X. Y. Xu and X. M. Jin, "Integrated Photonic Computing beyond the von Neumann Architecture," ACS Photonics, 2022

    work page 2022

  2. [13]

    Fluid learning: Mimicking brain computing with neuromorphic nanofluidic devices,

    A. Noy, Z. Li and S. B. Darling, "Fluid learning: Mimicking brain computing with neuromorphic nanofluidic devices," Nano Today, vol. 53, 2023

    work page 2023

  3. [14]

    Electrokinetic ion transport in nanofluidics and membranes with applications in bioanalysis and beyond,

    L. J. Cheng, "Electrokinetic ion transport in nanofluidics and membranes with applications in bioanalysis and beyond," Biomicrofluidics, vol. 12, no. 2, 2018

    work page 2018

  4. [1]

    Grundmann, The physics of semiconductors: An introduction including devices and nanophysics, 2006

    M. Grundmann, The physics of semiconductors: An introduction including devices and nanophysics, 2006

    work page 2006

  5. [2]

    FinFET—A self-aligned double-gate MOSFET scalable to 20 nm,

    D. Hisamoto, W. C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T. J. King, J. Jeffrey and C. Hu, "FinFET—A self-aligned double-gate MOSFET scalable to 20 nm," IEEE Transactions on Electron Devices, vol. 47, no. 12, 2000

    work page 2000

  6. [3]

    H. R. Huff, John Bardeen and transistor physics, 2003

    work page 2003

  7. [4]

    High-κ gate dielectrics: Current status and materials properties considerations,

    G. D. Wilk, R. M. Wallace and J. M. Anthony, "High-κ gate dielectrics: Current status and materials properties considerations," Journal of Applied Physics, vol. 89, no. 10, 2001

    work page 2001

  8. [5]

    A historical review of circuit simulation,

    D. Pederson, "A historical review of circuit simulation," IEEE Transactions on Circuits and Systems, vol. 31, no. 1, pp. 103--111, 1984

    work page 1984

Show all 59 references
  1. [6]

    Machine Learning for Electronic Design Automation: A Survey,

    G. Huang, J. Hu, Y. He, J. Liu, M. Ma, Z. Shen, J. Wu, Y. Xu, H. Zhang, K. Zhong, X. Ning, Y. Ma, H. Yang, B. Yu, H. Yang and Y. Wang, "Machine Learning for Electronic Design Automation: A Survey," ACM Transactions on Design Automation of Electronic Systems, vol. 26, no. 5, 9 2021

    2021

  2. [7]

    A FinFET with one atomic layer channel,

    M. L. Chen, X. Sun, H. Liu, H. Wang, Q. Zhu, S. Wang, H. Du, B. Dong, J. Zhang, Y. Sun, S. Qiu, T. Alava, S. Liu, D. M. Sun and Z. Han, "A FinFET with one atomic layer channel," Nature Communications, vol. 11, no. 1, 2020

    2020

  3. [8]

    Pushing the limits of lithography,

    T. Ito and S. Okazaki, "Pushing the limits of lithography," Nature, vol. 406, no. 6799, 2000

    2000

  4. [9]

    Makers of the Microchip: A Documentary History of Fairchild Semiconductor (review),

    M. Riordan, "Makers of the Microchip: A Documentary History of Fairchild Semiconductor (review)," Technology and Culture, vol. 52, no. 3, 2011

    2011

  5. [10]

    Roadmap for unconventional computing with nanotechnology,

    G. Finocchio, J. A. C. Incorvia, J. S. Friedman, Q. Yang, A. Giordano, J. Grollier, H. Yang, F. Ciubotaru, A. V. Chumak, A. J. Naeemi, S. D. Cotofana, R. Tomasello, C. Panagopoulos, M. Carpentieri, P. Lin, G. Pan, J. J. Yang, A. Todri-Sanial, G. Boschetto, K. Makasheva, V. K. ...

    2024

  6. [11]

    Scaling up molecular pattern recognition with DNA-based winner-take-all neural networks,

    K. M. Cherry and L. Qian, "Scaling up molecular pattern recognition with DNA-based winner-take-all neural networks," Nature, vol. 559, no. 7714, 2018

    2018

  7. [15]

    Effects of biological reactions and modifications on conductance of nanofluidic channels,

    R. Karnik, K. Castelino, R. Fan, P. Yang and A. Majumdar, "Effects of biological reactions and modifications on conductance of nanofluidic channels," Nano Letters, vol. 5, no. 9, 2005

    2005

  8. [16]

    Ionic Circuits Powered by Reverse Electrodialysis for an Ultimate Iontronic System,

    S. H. Han, S. R. Kwon, S. Baek and T. D. Chung, "Ionic Circuits Powered by Reverse Electrodialysis for an Ultimate Iontronic System," Scientific Reports, vol. 7, no. 1, 12 2017

    2017

  9. [17]

    Toward complementary ionic circuits: The npn ion bipolar junction transistor,

    K. Tybrandt, E. O. Gabrielsson and M. Berggren, "Toward complementary ionic circuits: The npn ion bipolar junction transistor," Journal of the American Chemical Society, vol. 133, no. 26, pp. 10141-10145, 7 2011

    2011

  10. [18]

    Chemical delivery array with millisecond neurotransmitter release,

    A. Jonsson, T. A. Sjöström, K. Tybrandt, M. Berggren and D. T. Simon, "Chemical delivery array with millisecond neurotransmitter release," Science Advances, vol. 2, no. 11, 2016

    2016

  11. [19]

    A multi-ion electrophoretic pump for simultaneous on-chip delivery of H+, Na+, and Cl-,

    M. Jia, M. Jafari, P. Pansodtee, M. Teodorescu, M. Gomez and M. Rolandi, "A multi-ion electrophoretic pump for simultaneous on-chip delivery of H+, Na+, and Cl-," APL Materials, vol. 10, no. 4, 2022

    2022

  12. [20]

    Nanofluidics coming of age,

    L. Bocquet, "Nanofluidics coming of age," Nature materials, vol. 19, no. 3, pp. 254-256, 3 2020

    2020

  13. [21]

    Logic gating of low-abundance molecules using polyelectrolyte- based diodes,

    B. Sabbagh, Z. Zhang and G. Yossifon, "Logic gating of low-abundance molecules using polyelectrolyte- based diodes," Faraday Discussions, vol. 246, 2023

    2023

  14. [22]

    Neuromorphic functions with a polyelectrolyte-confined fluidic memristor,

    T. Xiong, C. Li, X. He, B. Xie, J. Zong, Y. Jiang, W. Ma, F. Wu, J. Fei, P. Yu and L. Mao, "Neuromorphic functions with a polyelectrolyte-confined fluidic memristor," Science, vol. 379, no. 6628, 2023

    2023

  15. [23]

    Hybrid Circuits with Nanofluidic Diodes and Load Capacitors,

    P. Ramirez, V. Garcia-Morales, V. Gomez, M. Ali, S. Nasir, W. Ensinger and S. Mafe, "Hybrid Circuits with Nanofluidic Diodes and Load Capacitors," Physical Review Applied, vol. 7, no. 6, 2017

    2017

  16. [24]

    Bioinspired carbon nanotube–based nanofluidic ionic transistor with ultrahigh switching capabilities for logic circuits,

    W. Liu, T. Mei, Z. Cao, C. Li, Y. Wu, L. Wang, G. Xu, Y. Chen, Y. Zhou, S. Wang, Y. Xue, Y. Yu, X. Y. Kong, R. Chen, B. Tu and K. Xiao, "Bioinspired carbon nanotube–based nanofluidic ionic transistor with ultrahigh switching capabilities for logic circuits," Science Advances, ...

    2024

  17. [25]

    Concatenated logic functions using nanofluidic diodes with all-electrical inputs and outputs,

    V. Gomez, P. Ramirez, J. Cervera, M. Ali, S. Nasir, W. Ensinger and S. Mafe, "Concatenated logic functions using nanofluidic diodes with all-electrical inputs and outputs," Electrochemistry Communications, vol. 88, 2018. 19

    2018

  18. [26]

    High-Performance Integrated Iontronic Circuits Based on Single Nano/Microchannels,

    J. Li, M. Li, K. Zhang, L. Hu and D. Li, "High-Performance Integrated Iontronic Circuits Based on Single Nano/Microchannels," Small, vol. 19, no. 22, 2023

    2023

  19. [27]

    Ionic circuits based on poly electrolyte diodes on a microchip,

    J. H. Han, K. B. Kim, H. C. Kim and T. D. Chung, "Ionic circuits based on poly electrolyte diodes on a microchip," Angewandte Chemie - International Edition, vol. 48, no. 21, pp. 3830-3833, 5 2009

    2009

  20. [28]

    Designing with Iontronic Logic Gates─From a Single Polyelectrolyte Diode to an Integrated Ionic Circuit,

    B. Sabbagh, N. Fraiman, A. Fish and G. Yossifon, "Designing with Iontronic Logic Gates─From a Single Polyelectrolyte Diode to an Integrated Ionic Circuit," ACS Applied Materials and Interfaces, vol. 15, no. 19, 2023

    2023

  21. [29]

    The Synergy SPICE-Compact Models,

    A. Vladimirescu, "The Synergy SPICE-Compact Models," European Solid-State Device Research Conference, Vols. 2019-September, 2019

    2019

  22. [30]

    Cerebras Systems Unveils World’s Fastest AI Chip with Whopping 4 Trillion Transistors,

    Cerebras, "Cerebras Systems Unveils World’s Fastest AI Chip with Whopping 4 Trillion Transistors," March

  23. [31]

    CIRCUITS AND SYSTEMS A SHORT HISTORY OF

    F. Maloberti and A. C. Davies, "CIRCUITS AND SYSTEMS A SHORT HISTORY OF"

  24. [32]

    H.E.Weste and D

    N. H.E.Weste and D. M. Harris, CMOS VLSI Design: A Circuits and Systems Perspective (4th Edition), 2010

    2010

  25. [33]

    Yogesh Singh, L

    C. Yogesh Singh, L. Darsen, V. Sriramkumar, K. Sourabh, . D. Juan Pablo, P. Navid, . N. Ali and H. Chenming, FinFET modeling for IC simulation and design: using the BSIM-CMG standard, Academic Press, 2015

    2015

  26. [34]

    Tybrandt, K

    K. Tybrandt, K. C. Larsson, A. Richter-Dahlfors and M. Berggren, Ion bipolar junction transistors, vol. 107, 2010

    2010

  27. [35]

    Geometrically Scalable Iontronic Memristors: Employing Bipolar Polyelectrolyte Gels for Neuromorphic Systems,

    Z. Zhang, B. Sabbagh, Y. Chen and G. Yossifon, "Geometrically Scalable Iontronic Memristors: Employing Bipolar Polyelectrolyte Gels for Neuromorphic Systems," ACS nano, 2024

    2024

  28. [36]

    An Ionic Capacitor for Integrated Iontronic Circuits,

    P. Janson, E. O. Gabrielsson, K. J. Lee, M. Berggren and D. T. Simon, "An Ionic Capacitor for Integrated Iontronic Circuits," Advanced Materials Technologies, vol. 4, no. 4, 2019

    2019

  29. [37]

    Ion flow crossing over a polyelectrolyte diode on a microfluidic chip,

    J. H. Han, K. B. Kim, J. H. Bae, B. J. Kim, C. M. Kang, H. C. Kim and T. D. Chung, "Ion flow crossing over a polyelectrolyte diode on a microfluidic chip," Small, vol. 7, no. 18, pp. 2629-2639, 9 2011

    2011

  30. [38]

    Vladimirescu, The SPICE book, John Wiley \& Sons, Inc., 1994

    A. Vladimirescu, The SPICE book, John Wiley \& Sons, Inc., 1994

    1994

  31. [39]

    Short-term memory in electric double-layer capacitors,

    A. Allagui, D. Zhang and A. S. Elwakil, "Short-term memory in electric double-layer capacitors," Applied Physics Letters, vol. 113, no. 25, 2018

    2018

  32. [40]

    Modeling of memory effects in nanofluidic diodes,

    J. Cervera, S. Portillo, P. Ramirez and S. Mafe, "Modeling of memory effects in nanofluidic diodes," Physics of Fluids, vol. 36, no. 4, 2024

    2024

  33. [41]

    Best practices for compact modeling in Verilog-A,

    C. C. McAndrew, G. J. Coram, K. K. Gullapalli, J. R. Jones, L. W. Nagel, A. S. Roy, J. Roychowdhury, A. J. Scholten, G. D. Smit, X. Wang and others, "Best practices for compact modeling in Verilog-A," IEEE Journal of the Electron Devices Society, vol. 3, no. 5, pp. 383--396, 2015. 20

    2015

  34. [42]

    Fitzpatrick, Analog Design and Simulation Using OrCAD Capture and PSpice, 2017

    D. Fitzpatrick, Analog Design and Simulation Using OrCAD Capture and PSpice, 2017

    2017

  35. [43]

    A simple DNA gate motif for synthesizing large-scale circuits,

    L. Qian and E. Winfree, "A simple DNA gate motif for synthesizing large-scale circuits," Journal of the Royal Society Interface, vol. 8, no. 62, 2011

    2011

  36. [44]

    Integrated Iontronic Circuits Based on Single Nanochannels,

    J. Li and D. Li, "Integrated Iontronic Circuits Based on Single Nanochannels," ACS Applied Materials and Interfaces, vol. 13, no. 40, 2021. Methods For more detailed information on the diode structure, measurements and fabrication process, the reader is referred to our previou...

    2021

  37. [46]

    𝑅்௦௦ି =𝑅௘ +𝑅௣ି= 4.9 ∙ 10଻Ω 𝑉஽௜௢ௗ௘< 0

  38. [47]

    𝑉𝑐, the voltage across 𝑅௣(𝑉) and 𝐶௣(𝑉), was defined as the diode voltage (𝑉஽௜௢ௗ௘) minus the voltage drop across 𝑅௘, which was assumed to be constant in our model

    𝑅்௦௦ା =𝑅௘ +𝑅௣ା= 8.4 ∙ 10ହΩ 𝑉஽௜௢ௗ௘≥ 0 For simplicity we took the value at 0 to be equal to the total resistance for the forward bias. 𝑉𝑐, the voltage across 𝑅௣(𝑉) and 𝐶௣(𝑉), was defined as the diode voltage (𝑉஽௜௢ௗ௘) minus the voltage drop across 𝑅௘, which was assumed to be cons...

  39. [48]

    𝑅௘ = ௏೔೙ ூ೛೐ೌೖ = 5.5 ∙ 10ହ Ω This constraint served to calculate 𝑅௣ି and 𝑅௣ା from the first two equations

  40. [49]

    Given the electrical circuit described in Figure 2(b) the system can be described using the following single ordinary differential equation:

    𝑅௣ି= 4.84 ∙ 10଻ Ω Calibration of the voltage dependent capacitor parameters Each transition was measured twice to ensure repeatability. Given the electrical circuit described in Figure 2(b) the system can be described using the following single ordinary differential equation:

  41. [50]

    The analytical solution of the above differential equation is:

    ௗொ ௗ௧= ௏೔೙ ோ೐ − ொ ஼೛ ∙ ோ೐ାோ೛ ோ೛ோ೐ where Q represents the charge on the capacitance 𝐶௣ , and 𝑉௜௡ is the diode voltage. The analytical solution of the above differential equation is:

  42. [51]

    From equation [7] and the full relationship between Q and the current on 𝑅௘:

    𝑄=௏೔೙஼೛ோ೛ ோ೐ାோ೛ +𝐴∙𝑒ି൬ೃ೛శೃ೐ ಴೛ೃ೛ೃ೐൰௧ where A is a constant which is determined by the initial condition. From equation [7] and the full relationship between Q and the current on 𝑅௘:

  43. [52]

    𝐼ோ೐ =𝐼஼ +𝐼ோ೛ =ௗொ ௗ௧+௏೎ ோ೛ =ௗொ ௗ௧+ ொ ஼೛ோ೛ We get the general solution for the diode current (which is equal to the current on 𝑅௘):

  44. [53]

    𝐼ௗ௜௢ௗ௘=𝐼ோ೐ = ௏೔೙ ோ೐ାோ೛ − ஺ ஼ோ೐ ∙𝑒ି൬ೃ೛ శೃ೐ ಴೛ೃ೛ೃ೐൰௧ This predicts a growth / decay curve with a single time scale:

  45. [54]

    The current responses for the different step scenarios are plotted in Error! Reference source not found.(a)

    𝜏 =஼೛ோ೛ோ೐ ோ೛ାோ೐ Based on the model, we inferred the data using a single exponent. The current responses for the different step scenarios are plotted in Error! Reference source not found.(a). After normalizing by subtracting the steady state value from the signal measurement an...

  46. [55]

    In this figure, the original measurement was divided into four separate graphs, each isolating and highlighting the detailed behavior of an individual transition

    𝐼ௗ௜௢ௗ௘೘ೌ೙೔೛ೠೌ೗೟೐= ூ೏೔೚೏೐ିூೞೞ ூ೏೔೚೏೐(௧ୀ଴)ିூೞೞ = 𝑒ି൬ೃ೛శೃ೐ ಴೛ೃ೛ೃ೐൰௧ = 𝑒ି೟ ഓ Figure M 1: (a) Step-response measurements of the iontronic diode's current as a function of time for four different input voltage transitions presented above (Figure 3(a)). In this figure, the original m...

  47. [56]

    𝜏଴,ଵ =஼శோ೛శோ೐ ோ೛శାோ೐ = 71 𝑠𝑒𝑐

  48. [57]

    We assumed that this was the result of memory such that when moving from 1 to -1 the capacitor stayed at the 𝐶ା value, which should then follow the value:

    𝜏଴,ିଵ=஼షோ೛షோ೐ ோ೛షାோ೐ = 0.54 𝑠𝑒𝑐 Note that the timescale for the decay curve for a response from 0 to -1 was much shorter than the response to steps between 1 to -1. We assumed that this was the result of memory such that when moving from 1 to -1 the capacitor stayed at the 𝐶ା ...

  49. [58]

    Thus, to capture this experimental feature, more complexity needed to be added to the model

    𝜏ଵ,ିଵ=஼శோ೛షோ೐ ோ೛షାோ೐ However since 𝑅௣ା < 𝑅௣ି , according to Eq [12] and Eq [14] , 𝜏଴,ଵ < 𝜏ଵ,ିଵ, did not match the experimental value. Thus, to capture this experimental feature, more complexity needed to be added to the model. Given the calibrated values for the resistors, the...

  50. [59]

    Additionally, the LLM was employed to assist in developing scripts for visualizing simulation and experimental data

    𝐶ି = 9.93 ∙ 10ି଻[𝐹] large language model We acknowledge the use of a large language model (LLM) for grammar and improving the clarity of the language in this manuscript. Additionally, the LLM was employed to assist in developing scripts for visualizing simulation and experimental data

  51. [2024]

    Available: https://cerebras.ai/press-release/cerebras-announces-third-generation-wafer- scale-engine

    [Online]. Available: https://cerebras.ai/press-release/cerebras-announces-third-generation-wafer- scale-engine

Pith tools

Reviewed August 12, 2026 · model on record in the stance chip above.