AiEDA: Agentic AI Design Framework for Digital ASIC System Design

Aditya Patra; Arun Ravindran; Saroj Rout

REVIEW 5 major objections 5 minor 15 references

AiEDA: Agentic AI Design Framework for Digital ASIC System Design

T0 review · 5 major / 5 minor · reviewed 2026-08-11 · deepseek-v4-flash

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Pith's one-line read AiEDA proposes an agentic AI design flow that takes a digital ASIC from a natural-language specification to GDSII layout using open-source EDA tools.

desk verdict A clear, honest proposal for an agentic LLM-driven ASIC flow, but the abstract claims a demonstration the body does not provide: one unverifiable FIFO GDS run and an unfinished KWS design. read the letter →

arxiv 2412.09745 v1 pith:U7GUVAFR submitted 2024-12-12 cs.AR

Aditya Patra , Saroj Rout , Arun Ravindran This is my paper · ORCID

classification cs.AR

keywords agenticAIworkflowdigitalASICdesignlargelanguagemodelsHDLgenerationopen-sourceEDAGDSIIlayoutkeywordspottingretrieval-augmented

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper proposes AiEDA, an agentic design framework in which LLM agents coordinate open-source EDA tools across four stages—architecture, RTL, synthesis, and physical design—to take a digital ASIC from a natural-language specification to a GDSII layout ready for fabrication. If it works, chip designers would describe intent in words and let agents iterate with tool feedback until verification, timing, and design-rule checks pass, promising large productivity gains. The demonstration is preliminary: a simple 6-bit FIFO was taken from RTL to GDSII, and architectural exploration of an ultra-low-power keyword-spotting ASIC produced bandwidth and precision choices. The end-to-end KWS design is stated as ongoing work rather than completed.

What carries the argument

The load-bearing mechanism is the per-stage feedback loop between an LLM and an EDA tool: a design prompt or reflection prompt is given to the LLM, the LLM produces code or commands, the tool runs, and the tool output is fed back to the LLM for analysis and correction until the stage succeeds. The framework implements this loop in four stages: architecture (Python models and analysis scripts), RTL (Verilog generation with simulator feedback), synthesis (netlist generation with static timing feedback and LLM-generated corrective actions), and physical design (placement, routing, and GDSII generation). Retrieval-augmented generation supplies the LLM with relevant Verilog examples, and the designer can intervene at any point. The same loop is what would turn a specification into a layout without day-to-day expert involvement.

What would settle it

Take a non-trivial component, such as the keyword-spotting front-end, and run AiEDA end-to-end from prompt to GDSII without human RTL edits; then check whether the result passes design-rule and layout-vs-schematic checks, meets timing at the target frequency, and matches the architectural Python model. A run that requires expert manual fixes to close timing or clear DRC errors would show the loop has not closed autonomously.

Watch

Extended reading notes

Core claim

On the paper's own terms, the central claim is that an agentic design flow—an LLM that plans, invokes EDA tools, reads their feedback, and corrects itself in a loop—can carry a digital ASIC from a natural-language specification through architecture modeling, RTL generation and verification, synthesis and timing closure, and physical design to a GDSII layout. The authors demonstrate this with two parts: a completed but briefly reported run of a 6-bit, 32-depth FIFO from RTL to GDSII using the Sky130 process, and an architecture-stage exploration of an ultra-low-power keyword-spotting ASIC in which the LLM chose a 4 kHz bandwidth, 7-bit precision, a 32-point FFT, and shift-and-add coefficients. The paper is explicit that the full end-to-end KWS design is still in progress, so the claim about a fully autonomous flow is a proposal with preliminary support rather than a finished demonstration.

Load-bearing premise

That an LLM can keep driving the open-source EDA loop to clean, fabricatable results using only tool feedback and reflection prompts, with the designer stepping in occasionally rather than as a daily expert.

Editorial extensions

If this is right

A designer could start from a paragraph specification and obtain synthesizable, verified RTL plus a GDSII layout through an open-source toolchain, removing much of the tool-integration burden.
The self-correction loop could absorb routine simulation, timing, and design-rule fixes that currently consume expert time, letting designers focus on architectural trade-offs.
The architecture-stage loop can surface power, area, and accuracy trade-offs early, as it did for the KWS design's bandwidth and bit-width choices.
If the full flow completes, the same four-stage structure could serve as a template for other digital blocks, with each stage's tool feedback as the only requirement.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

Inference: The practical test of AiEDA is whether LLM-generated timing fixes generalize; a useful benchmark would compare agent corrections against expert fixes on a set of failing timing paths from real designs.
Inference: The framework's dependence on tool feedback means its ceiling is set by the quality of that feedback; structured summarization of long tool logs may be needed before LLM reasoning scales to designs with thousands of violations.
Inference: If the KWS design completes, the same agentic structure could extend beyond digital ASICs to verification and mixed-signal tasks, where feedback loops are less crisp and the opportunity for automation is large.
Inference: Because the completed FIFO run is reported without logs, timing reports, or DRC results, the GDSII claim should be read as a planned capability rather than a measured one.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

You should know two things about this paper. First, it is a genuine proposal, not a fake one: the authors describe a four-stage agentic flow (architecture, RTL, synthesis, physical design) that integrates LLM feedback loops with open-source tools, and they are upfront in the body that the work is ongoing. Second, the abstract oversells it. It says the framework is 'demonstrated' through an ultra-low-power KWS ASIC, but Section V.C admits the full end-to-end KWS design is still in progress, and the only complete GDS run is a 6-bit FIFO described in one sentence with no logs, no timing reports, no DRC output, no area or power numbers. What is actually new here is the integration. Prior work like AutoChip and GPT4AIChip stops at Verilog generation or FPGA HLS; AiEDA sketches a path from natural-language specification through synthesis, timing repair, and OpenROAD-based physical design to GDSII. The related work section is fair, and the authors correctly flag that bringing agentic AI into the physical-design feedback loops is future work. That honesty counts for something. The soft spots are real, and they are load-bearing. The claimed 5x power reduction from lowering bandwidth to 4 kHz and 2x area/power reduction from 7-bit precision are not backed by any simulation, measurement, power model, or baseline. The numbers may be plausible, but they are asserted. Similarly, the FIFO-to-GDS validation is unverifiable as reported. The LLM also serves as both generator and evaluator of design choices, which introduces a circularity that the paper does not address. None of this means the framework is impossible; it means the submitted evidence does not support the abstract's central claim. Who is this for? Researchers working on LLM-based EDA and anyone interested in agentic design flows. It reads like a workshop paper or a position statement. I would not cite it as a validated system, but I might bring it to a reading group to discuss the architecture and open questions. My recommendation: do not desk-reject out of hand - send it to referees, because the framework idea is important enough and plausible enough to merit careful review. But expect the reviewers to send it back for major revision, and tell the authors to release code, provide the FIFO artifacts, and complete the KWS run before claiming a demonstration.

Referee Report

5 major / 5 minor

Summary. The paper proposes AiEDA, an agentic AI framework intended to guide digital ASIC design from a natural-language specification through architecture exploration, RTL generation, synthesis, and physical design to GDSII using open-source tools. The framework is organized into four phases: architecture design (LLM-driven Python modeling and reflection), RTL design (LLM-generated Verilog with Icarus simulation feedback), netlist synthesis (Yosys and OpenSTA with LLM-assisted timing fixes), and physical design (OpenROAD and Magic). The authors present a keyword spotting (KWS) case study in which an LLM selects a 4 kHz audio bandwidth, 7-bit fixed-point precision, a 32-point FFT, shift-based coefficients, and rectangular Mel filters. The only reported RTL-to-GDSII result is a 6-bit, 32-depth FIFO, described in one sentence. The paper states that the full KWS end-to-end flow is still in progress.

Significance. If validated, AiEDA would extend LLM-based hardware design beyond HDL generation toward an integrated open-source design flow, and the KWS architecture exploration is a plausible demonstration vehicle. The paper provides a clear survey of related work (DAVE, Verigen, ChipNeMo, MG-Verilog, GPT4AIChip, AutoChip) and a systematic presentation of the proposed framework. However, the contribution is currently a proposal: the central demonstration is incomplete, the single GDSII run lacks all supporting artifacts, and the physical-design phase is explicitly not yet agentic. No code, logs, timing reports, or quantitative measurements are provided, so the reported area/power benefits cannot be assessed. The paper's honest disclosure of its status does not compensate for the absence of evidence for the abstract's claim of a demonstrated end-to-end flow.

major comments (5)

[Abstract and Section V.C] The abstract states that AiEDA is 'demonstrated through the design of an ultra-low-power digital ASIC for KeyWord Spotting,' but Section V.C says the full end-to-end KWS design is 'still in progress' and that the goal is to complete it before the conference date. No GDSII result, netlist, timing report, or power report for the KWS design appears anywhere in the manuscript. The central claim of a demonstrated concept-to-GDSII flow is therefore unsupported by the body of the paper.
[Section V.A] The only RTL-to-GDSII validation is a single sentence describing a 6-bit, 32-depth FIFO: 'The design process began with a prompt specifying the FIFO's requirements and concluded with the generation of the GDSII layout.' No RTL listing, synthesis script, OpenSTA timing report, DRC/LVS result, or area/power number is provided. Without these artifacts, the reader cannot verify that the flow completed successfully, that the GDSII is clean, or that agentic LLM control, rather than manual intervention, produced the result.
[Section III, Physical design] The Physical design phase explicitly states: 'Integrating agentic AI into these feedback loops is a potential area for future exploration.' Thus the current framework does not apply agentic AI to placement, clock tree synthesis, routing, or DRC closure. As a result, the paper's framing of AiEDA as an agentic flow that 'streamline[s] the transition from conceptual design to GDSII layout' overstates what is implemented; at most, the agentic portion covers architecture, RTL, and synthesis, with backend physical design performed by conventional OpenROAD/Magic tool flows.
[Section V.B] The quantitative architectural claims are not supported by any simulation or measurement. The paper asserts that a 4 kHz bandwidth 'will lead to an approximately 5x reduction in power consumption' and that 7-bit precision 'will yield around a 2x reduction in both area and power consumption,' but no power model, synthesis results, baseline comparison, or measurement is presented. Likewise, the statements that spectral leakage is 'limited to 10%' and that a 32-point FFT keeps accuracy loss 'within 25%' are given without plots, scripts, or evaluation data. These numbers may be reasonable estimates, but they are not demonstrated results.
[Section III, RTL design] The RTL design loop is described as repeated until 'functional verification is successful,' but the test benches are also generated by the LLM, and no independent verification, coverage results, or assertion-based checks are reported. The framework's reliance on LLM self-reflection as the sole correctness mechanism is a correctness-risk concern; a concrete test would be to provide a separately authored testbench or formal property suite, neither of which appears in the manuscript.

minor comments (5)

[Section V.A] The phrase 'refer to Figure Section III' is ambiguous; it should refer to a specific figure or section, e.g., Section III or Figure 2.
[Section VI] 'Reinforcement Learining with Human Feedback' contains a typo; it should be 'Learning'.
[Reference [3]] The URL in reference [3] contains a duplicated and mangled segment ('agentic-wagentic...orkflows'); it should be a single clean URL.
[Introduction] The phrase 'design of a ultra low power digital ASIC' should be 'design of an ultra-low-power digital ASIC' for grammatical correctness.
[Section V] The authors state that the design tools are 'still in active development' and that the project will be released as open-source once stable; adding a public repository or appendix with the FIFO scripts would strengthen reproducibility.

Circularity Check

0 steps flagged · score 0.0 of 10

No circular derivation chain: AiEDA is a framework proposal with preliminary, unfinished evaluation; no fitted parameter is relabeled as a prediction.

full rationale

The paper does not contain a mathematical derivation whose conclusion is equivalent to its inputs by construction. The central claims are architectural and experimental: AiEDA is a proposed agentic workflow around external open-source EDA tools, and the evidence is a one-sentence FIFO GDS run plus an unfinished KWS architectural exploration. There is no fitted parameter subsequently renamed as a prediction. In Section V.B, the LLM proposes design choices such as a 4 kHz bandwidth and 7-bit precision against explicit thresholds given in reflection prompts, and the paper states these were checked with Python-based spectral analysis. This is methodologically weak because the LLM acts as both generator and evaluator, and Section V.C explicitly says the full end-to-end KWS flow is 'still in progress,' so the abstract's claim that the framework is demonstrated through a KWS ASIC is not yet supported. However, that is an evidentiary/overclaiming issue, not circularity. The EDA tools (Icarus, Yosys, OpenSTA, OpenROAD, Magic) are external, non-LLM sources of feedback, and no load-bearing argument rests on a self-citation or on a uniqueness theorem imported from the authors. Therefore, no specific circular step can be exhibited, and the appropriate finding is no significant circularity.

Assumptions & free parameters 6 free parameters · 4 assumptions · 0 invented entities

The framework's claims rest on LLM-selected design parameters and on the unshown reliability of the open-source toolchain under agent control. None of the selected numbers is accompanied by measurements, baselines, or released artifacts, and the end-to-end KWS system is explicitly unfinished.

free parameters (6)

pre-emphasis alpha = 31/32 (0.969)
LLM-selected so the HPF uses a shift-and-add implementation; claimed to leave DC bins insignificant, but no spectrum measurement is shown. Entered at Eq. 1 in Section IV.
audio bandwidth = 4 kHz
LLM-selected to retain at least 90% of signal power; used to claim roughly 5x power reduction from the lower Nyquist rate. No measured power analysis is provided.
ADC bit precision = 7-bit fixed point
LLM-selected for area and power versus accuracy; claimed to give about 2x reduction in both, with no measurement or simulation shown.
FFT size = 32-point
LLM-selected as the minimum size within a 25% accuracy-loss threshold. No independent spectrogram or accuracy comparison is given.
Hanning window coefficients = fixed-point shift approximations
Selected by the LLM to keep spectral leakage at or below 10%; the leakage analysis is not quantified in the paper.
Mel filter shape = rectangular bins
Chosen over triangular bins with a claimed slight accuracy reduction; the trade-off is not measured.

assumptions (4)

domain assumption The open-source toolchain (Icarus, Yosys, OpenSTA, OpenROAD, Magic) can produce a valid GDSII layout from LLM-generated RTL with only scripted feedback.
Invoked throughout Section III and Section V.A; the only support is a one-sentence FIFO run with no logs or DRC output.
ad hoc to paper LLM reflection on simulator and analysis outputs is a sufficient verification mechanism for architectural and RTL correctness.
The framework lets the same LLM that generates code also judge the results of that code, as described in Section III and Section V.B.
domain assumption Automatically generated Verilog from natural-language prompts can reach functional closure through iterative tool feedback.
The RTL loop repeatedly sends simulator errors back to the LLM until functional verification passes, but no pass rates or corrected examples are reported.
domain assumption Magic-generated GDSII with the Sky130 PDK is fabrication-ready without additional signoff steps.
Section V.A concludes the FIFO flow with GDSII generation, but no design rule check, antenna check, or tapeout-related verification is reported.

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Cite this review

Pith. "Pith review of AiEDA: Agentic AI Design Framework for Digital ASIC System Design." pith.science (2026). https://pith.science/paper/U7GUVAFR

@misc{pith2026241209745,
  author       = {Pith},
  title        = {Pith review of: AiEDA: Agentic AI Design Framework for Digital ASIC System Design},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/U7GUVAFR}},
  note         = {Machine review of arXiv:2412.09745}
}

read the original abstract

The paper addresses advancements in Generative Artificial Intelligence (GenAI) and digital chip design, highlighting the integration of Large Language Models (LLMs) in automating hardware description and design. LLMs, known for generating human-like content, are now being explored for creating hardware description languages (HDLs) like Verilog from natural language inputs. This approach aims to enhance productivity and reduce costs in VLSI system design. The study introduces "AiEDA", a proposed agentic design flow framework for digital ASIC systems, leveraging autonomous AI agents to manage complex design tasks. AiEDA is designed to streamline the transition from conceptual design to GDSII layout using an open-source toolchain. The framework is demonstrated through the design of an ultra-low-power digital ASIC for KeyWord Spotting (KWS). The use of agentic AI workflows promises to improve design efficiency by automating the integration of multiple design tools, thereby accelerating the development process and addressing the complexities of hardware design.

Figures

Figures reproduced from arXiv: 2412.09745 by the authors.

**Figure 2.** Proposed agentic AI design framework for digital ASIC design. The design flow is broadly divided into four parts: 1) Architecture design (shaded [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗

**Figure 3.** Keyword Spotter (KWS) architecture. In this Section, we describe a case study of the application of our proposed design framework to the design of a digital keyword spotter system. Acoustic audio analysis is widely applied in critical areas such as heart monitoring, keyword spotting (KWS), and the preventive maintenance of heavy machinery [12]. Among these applications, KWS is essential for voice-activated assistant… view at source ↗

Discussion (0). Continue with ORCID to comment.

Reference graph

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