Paper Citation Record · LEDGER

Spiking Neural Network Accelerator Architecture for Differential-Time Representation using Learned Encoding

As of 20 August 2026, this Paper Citation Record lists 25 of 25 outbound references and 1 inbound Pith citation observation for arXiv:2501.07952.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2501.07952 v1

Coverage vector

measured 25 of 25 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-08-10T20:34:48.833989Z

measured 26 of 26 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-20T06:33:59.587034+00:00

measured 1 of 1 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-08-15T21:04:45.102909Z

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: pith, observed 2026-08-15T21:04:45.796756Z

Reference resolution

25 of 25 outbound references displayed

verified exact3
verified fuzzy16
unresolved5
parse uncertain0
malformed identifier0
metadata mismatch1

External citation measurements

No source-named external measurement is stored.

Outbound references

Observation c0e78bff-cd18-4876-bae4-1ccbb5a836b4 · outbound

This paper cites MNIST Handwritten Digit Database,.

Spiking Neural Network Accelerator Architecture for Differential-Time Representation using Learned Encoding MNIST Handwritten Digit Database,

Reference 1

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T20:34:49.173517Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.

Observation 33a33b72-648f-41f2-982b-34b28416e550 · outbound

This paper cites The Heidelberg spiking datasets for the systematic evaluation of spiking neural networks.

Spiking Neural Network Accelerator Architecture for Differential-Time Representation using Learned Encoding The Heidelberg spiking datasets for the systematic evaluation of spiking neural networks

Reference 2

Resolution: verified exact; local_arxiv, observed 2026-08-10T20:34:48.962286Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.

Observation 71a7913b-cd8e-4d81-ade3-b1c740407fee · outbound

This paper cites Speech Commands: A Dataset for Limited-Vocabulary Speech Recognition.

Spiking Neural Network Accelerator Architecture for Differential-Time Representation using Learned Encoding Speech Commands: A Dataset for Limited-Vocabulary Speech Recognition

Reference 3

Resolution: unresolved; no resolver link, observed 2026-08-10T20:34:48.742221Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 8fced5c0-57b6-4fd9-a711-6a0300acf0e3 · outbound

This paper cites Darwin: A neuromorphic hardware co-processor based on spiking neural networks,.

Spiking Neural Network Accelerator Architecture for Differential-Time Representation using Learned Encoding Darwin: A neuromorphic hardware co-processor based on spiking neural networks,

Reference 4

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T20:34:49.162003Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.

Observation d396a1c2-43a1-43e8-bc44-18604570d927 · outbound

This paper cites Energy efficient parallel neuromorphic architectures with approximate arithmetic on fpga,.

Spiking Neural Network Accelerator Architecture for Differential-Time Representation using Learned Encoding Energy efficient parallel neuromorphic architectures with approximate arithmetic on fpga,

Reference 5

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T20:34:49.149187Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.

Observation 08759d7f-e422-4400-a018-f1072b7cf8ca · outbound

This paper cites Advancing neuromorphic com- puting with loihi: A survey of results and outlook,.

Spiking Neural Network Accelerator Architecture for Differential-Time Representation using Learned Encoding Advancing neuromorphic com- puting with loihi: A survey of results and outlook,

Reference 6

Resolution: unresolved; no resolver link, observed 2026-08-10T20:34:48.755196Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation e6fbee70-868c-4907-b2ae-05077e290c9a · outbound

This paper cites Scalable noc-based neuro- morphic hardware learning and inference,.

Spiking Neural Network Accelerator Architecture for Differential-Time Representation using Learned Encoding Scalable noc-based neuro- morphic hardware learning and inference,

Reference 7

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T20:34:49.129067Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.

Observation 805eeeb7-f8b3-4662-8f9a-653ae0f09345 · outbound

This paper cites Snava—a real-time multi-fpga multi-model spiking neural network simulation architecture,.

Spiking Neural Network Accelerator Architecture for Differential-Time Representation using Learned Encoding Snava—a real-time multi-fpga multi-model spiking neural network simulation architecture,

Reference 8

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T20:34:49.116047Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.

Observation 42ceb4d0-d633-4ef7-a785-8965d953115b · outbound

This paper cites A Fast and Energy-Efficient SNN Processor With Adaptive Clock/Event-Driven Computation Scheme and Online Learning,.

Spiking Neural Network Accelerator Architecture for Differential-Time Representation using Learned Encoding A Fast and Energy-Efficient SNN Processor With Adaptive Clock/Event-Driven Computation Scheme and Online Learning,

Reference 9

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T20:34:49.103592Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.

Observation 19da4879-403e-4315-9e58-cc8be83dee00 · outbound

This paper cites Truenorth: Design and tool flow of a 65 mw 1 million neuron programmable neurosynaptic chip,.

Spiking Neural Network Accelerator Architecture for Differential-Time Representation using Learned Encoding Truenorth: Design and tool flow of a 65 mw 1 million neuron programmable neurosynaptic chip,

Reference 10

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T20:34:49.091996Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.

Observation d9aa8ba4-7c8e-428c-a14d-2b8004707cf3 · outbound

This paper cites A low power and low latency fpga-based spiking neural network accelerator,.

Spiking Neural Network Accelerator Architecture for Differential-Time Representation using Learned Encoding A low power and low latency fpga-based spiking neural network accelerator,

Reference 11

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T20:34:49.080728Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.

Observation 477dcaea-2580-4969-af15-ebc7161a8bdc · outbound

This paper cites The spinnaker project,.

Spiking Neural Network Accelerator Architecture for Differential-Time Representation using Learned Encoding The spinnaker project,

Reference 12

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T20:34:49.068693Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.

Observation 46ac4b4a-47bc-4165-9a53-4cdb4913ee56 · outbound

This paper cites SNN Architecture for Differential Time Encoding Using Decoupled Processing Time.

Spiking Neural Network Accelerator Architecture for Differential-Time Representation using Learned Encoding SNN Architecture for Differential Time Encoding Using Decoupled Processing Time

Reference 13

Resolution: verified exact; local_arxiv, observed 2026-08-10T20:34:48.929545Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.

Observation 1eb7514d-9102-4fd7-8347-774121880d0a · outbound

This paper cites Attention Is All You Need.

Spiking Neural Network Accelerator Architecture for Differential-Time Representation using Learned Encoding Attention Is All You Need

Reference 14

Resolution: unresolved; no resolver link, observed 2026-08-10T20:34:48.786711Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 43debcb5-ed36-4283-a3c4-2dd830baa901 · outbound

This paper cites An optimized multi-layer spiking neural network implementation in fpga without multipliers,.

Spiking Neural Network Accelerator Architecture for Differential-Time Representation using Learned Encoding An optimized multi-layer spiking neural network implementation in fpga without multipliers,

Reference 15

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T20:34:49.056391Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.

Observation cec1a921-aa00-4414-987e-55391ecd8367 · outbound

This paper cites Spiker+: a framework for the generation of efficient Spiking Neural Networks FPGA accelerators for inference at the edge.

Spiking Neural Network Accelerator Architecture for Differential-Time Representation using Learned Encoding Spiker+: a framework for the generation of efficient Spiking Neural Networks FPGA accelerators for inference at the edge

Reference 17

Resolution: unresolved; no resolver link, observed 2026-08-10T20:34:48.802598Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation ca8d8176-37ed-47aa-9dfc-eb9ecc85f441 · outbound

This paper cites Minitaur, an event-driven fpga-based spiking network accelerator,.

Spiking Neural Network Accelerator Architecture for Differential-Time Representation using Learned Encoding Minitaur, an event-driven fpga-based spiking network accelerator,

Reference 18

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T20:34:49.044862Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.

Observation e0300389-d4cd-4f36-aabc-62fd637cbb2d · outbound

This paper cites Fast and low-power leading-one detectors for energy-efficient logarithmic computing,.

Spiking Neural Network Accelerator Architecture for Differential-Time Representation using Learned Encoding Fast and low-power leading-one detectors for energy-efficient logarithmic computing,

Reference 19

Resolution: verified exact; doi, observed 2026-08-10T20:34:48.869818Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.

Observation c27c510f-294c-40dd-ac4d-fc935f8fb4af · outbound

This paper cites Leading one detectors and leading one position detectors - an evolutionary design methodology,.

Spiking Neural Network Accelerator Architecture for Differential-Time Representation using Learned Encoding Leading one detectors and leading one position detectors - an evolutionary design methodology,

Reference 20

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T20:34:49.033106Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.

Observation da7c0f00-5eeb-4b5d-986e-ca55116d4ea3 · outbound

This paper cites Vlsi implementations of low-power leading-one detector circuits,.

Spiking Neural Network Accelerator Architecture for Differential-Time Representation using Learned Encoding Vlsi implementations of low-power leading-one detector circuits,

Reference 21

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T20:34:49.020701Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.

Observation 840e8364-d9e8-4ce1-a885-a8af6cd3cab9 · outbound

This paper cites Approximate leading one detector design for a hardware-efficient mitchell multiplier,.

Spiking Neural Network Accelerator Architecture for Differential-Time Representation using Learned Encoding Approximate leading one detector design for a hardware-efficient mitchell multiplier,

Reference 22

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T20:34:49.008454Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.

Observation e3d67018-3f6c-4bf6-a14e-f701e64c7e9d · outbound

This paper cites Training spiking neural networks using lessons from deep learning,.

Spiking Neural Network Accelerator Architecture for Differential-Time Representation using Learned Encoding Training spiking neural networks using lessons from deep learning,

Reference 23

Resolution: unresolved; no resolver link, observed 2026-08-10T20:34:48.826371Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 3fefe26e-32cd-4ffc-9fe3-6d1acfd717b3 · outbound

This paper cites Syncnn: Evaluating and accel- erating spiking neural networks on fpgas,.

Spiking Neural Network Accelerator Architecture for Differential-Time Representation using Learned Encoding Syncnn: Evaluating and accel- erating spiking neural networks on fpgas,

Reference 24

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T20:34:48.987605Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.

Observation 7bbfc2ed-bbb9-43a8-8c36-316bf175f056 · outbound

This paper cites Encoding, model, and architecture: Systematic optimization for spiking neural network in fpgas,.

Spiking Neural Network Accelerator Architecture for Differential-Time Representation using Learned Encoding Encoding, model, and architecture: Systematic optimization for spiking neural network in fpgas,

Reference 25

Resolution: verified fuzzy; raw_fallback, observed 2026-08-10T20:34:48.974991Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.

Observation e332128e-b61c-48ff-a412-f0534366bac9 · outbound

This paper cites Spiker: an FPGA-optimized Hardware acceleration for Spiking Neural Networks.

Spiking Neural Network Accelerator Architecture for Differential-Time Representation using Learned Encoding Spiker: an FPGA-optimized Hardware acceleration for Spiking Neural Networks

Reference 2022

Resolution: metadata mismatch; local_arxiv, observed 2026-08-10T20:34:48.899278Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.

Pith citing papers

Observation 3c1d4fb8-e26d-4f1d-bc1c-ebb068bb0aae · inbound

Lightweight LIF-only SNN accelerator using differential time encoding cites this paper.

Lightweight LIF-only SNN accelerator using differential time encoding Spiking Neural Network Accelerator Architecture for Differential-Time Representation using Learned Encoding

Reference 5

Resolution: verified exact; local_arxiv, observed 2026-08-15T21:04:45.801704Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-20T06:33:59.587034+00:00.