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arxiv: 2501.16205 · v3 · pith:35HIG2FXnew · submitted 2025-01-27 · 💻 cs.DC · cs.AR

EPOCH: Enabling Preemption Operation for Context Saving in Heterogeneous FPGA Systems

Arsalan Ali Malik , Emre Karabulut , Aydin Aysu This is my paper

Pith reviewed 2026-05-23 04:46 UTC · model grok-4.3

classification 💻 cs.DC cs.AR
keywords FPGA preemptioncontext savingmulti-tenant FPGAstate snapshottask resumptioncloud FPGAheterogeneous systemsZynq SoC
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The pith

EPOCH lets FPGA tasks stop at any clock cycle, save their full state to off-chip memory, and resume later without restarting.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper presents EPOCH as a ready-to-use framework that interrupts FPGA tasks in shared cloud systems at any chosen clock cycle, reads out the complete internal state of logic blocks, memory, and processing units, and writes a snapshot to external memory. When the task needs to continue, the framework writes the saved values back so execution picks up exactly where it left off. This addresses the missing preemption support on FPGAs that already exists for CPUs, allowing the operating system to manage FPGA resources without forcing tasks to start over after each interruption. The method automates the extraction and restoration steps and keeps all logic in one clock domain to avoid timing problems during the save and restore operations.

Core claim

EPOCH is the first out-of-the-box framework that can interrupt a tenant's execution at any arbitrary clock cycle, capture its state, save this state snapshot in off-chip memory with fine-grain granularity, and later resume execution from the saved snapshot, all while automating the processes, shielding users from complexities, and synchronizing logic in a common clock domain to prevent timing violations.

What carries the argument

Automated cycle-accurate state extraction and restoration for FPGA elements including LUTs, flip-flops, BRAMs, and DSP units, performed via frame-level operations synchronized in a single clock domain.

If this is right

  • FPGA tasks in multi-tenant clouds can be switched without context loss or restart, enabling the OS to balance resources the same way it does for CPU tasks.
  • Context save takes 62.2 microseconds and restore takes 67.4 microseconds per frame on the tested ZynQ device.
  • The framework works on existing FPGA hardware and tool flows without vendor modifications.
  • All fundamental FPGA resources (LUTs, flip-flops, BRAMs, DSPs) are covered by the snapshot process.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Operating systems could treat FPGA accelerators as preemptible resources comparable to CPU threads, changing how cloud schedulers allocate hardware.
  • The approach might reduce wasted FPGA time when a higher-priority task arrives, lowering the cost of sharing one chip among many users.
  • Future designs could combine this state snapshot method with partial reconfiguration to move tasks between different FPGA regions without data loss.

Load-bearing premise

The FPGA fabric and standard design tools allow reading and writing the entire internal state at any chosen cycle without adding timing violations or needing changes from the chip vendor.

What would settle it

Running a design on the ZynQ-XC7Z020, stopping it at a random cycle, saving and restoring the state, then checking whether the resumed output matches the uninterrupted run at the same number of cycles afterward.

Figures

Figures reproduced from arXiv: 2501.16205 by Arsalan Ali Malik, Aydin Aysu, Emre Karabulut.

Figure 1
Figure 1. Figure 1: An example illustrating preemption support in a multi-tenant FPGA [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: The configuration logic block (CLB) of Xilinx [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Block diagram of EPOCH on the Xilinx Zynq SoC with EPOCH [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: The frame format for two different configurations: (a) frame readback [PITH_FULL_IMAGE:figures/full_fig_p006_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Visualization of the frame and configuration bit layout within the Xilinx Zynq [PITH_FULL_IMAGE:figures/full_fig_p007_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: The two FPGA layouts employed in our experiments for (a) basic and [PITH_FULL_IMAGE:figures/full_fig_p008_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: The operational workflow of EPOCH consists of four steps. (1) The [PITH_FULL_IMAGE:figures/full_fig_p009_7.png] view at source ↗
read the original abstract

FPGAs are increasingly used in multi-tenant cloud environments to offload compute-intensive tasks from the main CPU. The operating system (OS) plays a vital role in identifying tasks suitable for offloading and coordinating between the CPU and FPGA for seamless task execution. The OS leverages preemption to manage CPU efficiently and balance CPU time; however, preempting tasks running on FPGAs without context loss remains challenging. Despite growing reliance on FPGAs, vendors have yet to deliver a solution that fully preserves and restores task context. This paper presents EPOCH, the first out-of-the-box framework to seamlessly preserve the state of tasks running on multi-tenant cloud FPGAs. EPOCH enables interrupting a tenant's execution at any arbitrary clock cycle, capturing its state, and saving this 'state snapshot' in off-chip memory with fine-grain granularity. Subsequently, when task resumption is required, EPOCH can resume execution from the saved 'state snapshot', eliminating the need to restart the task from scratch. EPOCH automates intricate processes, shields users from complexities, and synchronizes all underlying logic in a common clock domain, mitigating timing violations and ensuring seamless handling of interruptions. EPOCH proficiently captures the state of fundamental FPGA elements, such as look-up tables, flip-flops, block--RAMs, and digital signal processing units. On real hardware, ZynQ-XC7Z020 SoC, the proposed solution achieves context save and restore operations per frame in 62.2us and 67.4us, respectively.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The paper presents EPOCH, an out-of-the-box framework for enabling preemption on multi-tenant FPGAs by allowing interruption of tenant execution at any arbitrary clock cycle, capturing the full internal state (LUTs, flip-flops, BRAMs, DSPs) into a snapshot saved in off-chip memory, and later resuming from that snapshot. It automates the process, synchronizes logic to a common clock domain to avoid timing issues, and reports context save/restore times of 62.2 µs and 67.4 µs per frame on a ZynQ-XC7Z020 device.

Significance. If the central claims hold with proper verification, EPOCH would address a key gap in FPGA cloud computing by enabling true preemption without task restart, improving resource utilization in multi-tenant settings. The use of real hardware measurements on a ZynQ device is a positive aspect, providing concrete timing data rather than simulation-only results.

major comments (2)
  1. [Abstract] Abstract: The claim of enabling interruption 'at any arbitrary clock cycle' with cycle-accurate state capture is load-bearing for the contribution, yet the reported metrics are given only as per-frame times with no accompanying timing reports, clock-skew analysis, or description of how readback is triggered without introducing violations that could invalidate the snapshot.
  2. [Abstract] Abstract: No verification steps, error bars, or exclusion criteria are described for confirming that a restored snapshot produces identical results to an uninterrupted execution; this is required to substantiate that the capture process itself does not corrupt state for LUTs, FFs, BRAMs, or DSPs.
minor comments (1)
  1. [Abstract] Abstract: Typo in 'block--RAMs' (double dash).

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive feedback. We address each major comment below.

read point-by-point responses

  1. Referee: [Abstract] Abstract: The claim of enabling interruption 'at any arbitrary clock cycle' with cycle-accurate state capture is load-bearing for the contribution, yet the reported metrics are given only as per-frame times with no accompanying timing reports, clock-skew analysis, or description of how readback is triggered without introducing violations that could invalidate the snapshot.

    Authors: The abstract states that EPOCH synchronizes all logic to a common clock domain to mitigate timing violations. We acknowledge that explicit timing reports, clock-skew analysis, and a description of the readback trigger mechanism would better substantiate the cycle-accurate claim. We will add these details in the revision. revision: yes

  2. Referee: [Abstract] Abstract: No verification steps, error bars, or exclusion criteria are described for confirming that a restored snapshot produces identical results to an uninterrupted execution; this is required to substantiate that the capture process itself does not corrupt state for LUTs, FFs, BRAMs, or DSPs.

    Authors: The manuscript reports successful hardware execution on the ZynQ device, which implies verification occurred. To address the concern directly, we will revise the paper to include an explicit description of the verification methodology, including any error bars and criteria applied to confirm identical results for LUTs, FFs, BRAMs, and DSPs. revision: yes

Circularity Check

0 steps flagged

Implementation paper with no derivation chain or fitted predictions

full rationale

This is an implementation and measurement paper describing a framework for FPGA context saving and preemption. The abstract and provided text contain no equations, no fitted parameters, no self-citations used as load-bearing for a derivation, and no predictions that reduce to inputs by construction. The central claims are supported by hardware measurements on ZynQ-XC7Z020 (e.g., 62.2 µs / 67.4 µs per frame), making the work self-contained against external benchmarks with no circular steps present.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

This is a systems implementation paper; no free parameters, mathematical axioms, or new postulated entities are introduced.

pith-pipeline@v0.9.0 · 5818 in / 1156 out tokens · 34043 ms · 2026-05-23T04:46:31.795094+00:00 · methodology

discussion (0)

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