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REVIEW 5 major objections 5 minor 27 references

A Tensor-Train Decomposition based Compression of LLMs on Group Vector Systolic Accelerator

T0 review · 5 major / 5 minor · reviewed 2026-08-09 · deepseek-v4-flash

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Pith's one-line read Tensor-train decomposition of linear layers, paired with a group-vector systolic array and DSP-shared FP16 x INT4 PEs, lets ChatGLM3-6B and LLaMA2-7B fit on an FPGA and cuts first-token delay by 1.45x and 1.57x.

desk verdict Solid TTD-on-FPGA engineering, but the LLaMA2-7B timing and CR tables don't add up and the speedup claim needs board measurements. read the letter →

arxiv 2501.19135 v1 pith:EJF5JN4V submitted 2025-01-31 cs.AR

Sixiao Huang , Tintin Wang , Ang Li , Ao Shen , Kai Li , Keyao Jiang , Mingqiang Huang , Hao Yu This is my paper · ORCID
classification cs.AR
keywords tensor-traindecompositionLLMcompressionFPGAacceleratorsystolicarraylinearlayerfirst-tokenlatencyChatGLM3LLaMA2
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper claims that tensor-train decomposition (TTD) can compress the linear layers of 6B- and 7B-scale LLMs enough for FPGA deployment, and that a systolic array built for TTD inference makes the compressed model faster than the same accelerator running the uncompressed network. Applying TTD to selected transformer blocks gives whole-network compression ratios of 1.94x for ChatGLM3-6B and 1.60x for LLaMA2-7B, with C-Eval score down 4.21 and C4 perplexity up 2.62. On the group-vector systolic array with DSP-shared FP16 x INT4 processing elements, first-token delay falls by 1.45x and 1.57x relative to the same accelerator without TTD inference. This matters because it offers a concrete path to billion-parameter LLM inference on resource-constrained hardware without relying on sparsity or aggressive quantization alone.

What carries the argument

The load-bearing object is the tensor-train decomposition itself: the compressed form is a chain of low-rank cores $G_k$, and TTD inference multiplies the tensorized input through those cores one at a time, summing over each input dimension in sequence. The group-vector systolic array (GVSA) executes these contractions, using DSP-shared parallel vector processing elements that pack two INT4 weights with one FP16 feature into a single 27x18 DSP multiplier, so the compute runs as FP16 x INT4 without dedicated FP16 multipliers. The reordering needed between TTD stages is hidden by writing each intermediate $P_k$ into ping-pong buffers along a block dimension and an address dimension, then reading across blocks so that the next stage sees the data already in the required layout.

What would settle it

Run the same TTD-compressed ChatGLM3-6B and LLaMA2-7B designs on a physical V80 FPGA and compare end-to-end first-token delays against the emulated 14.34ms and 15.20ms; if the no-TTD baseline is not slower by the claimed 1.45x/1.57x, or if the TTD blocks become memory-bound under real HBM contention, the central speedup claim fails.

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Extended reading notes

Core claim

The central discovery is that tensor-train decomposition of linear-layer weight matrices is compatible with high-throughput systolic-array inference, and the combination produces measurable end-to-end latency gains on an FPGA-class accelerator. The paper tensorizes each linear weight $W$ into a $d$-dimensional tensor, factorizes it into rank-16 cores $G_1,\ldots,G_d$, and computes output $Y$ by sequential contractions $P_k[t_{k-1},j_k]=\sum_{i_k} G_k[i_k,j_k]P_{k-1}[i_k,t_{k-1}]$, reordering the intermediate $P_k$ in ping-pong buffers between stages. With TTD applied to 15 blocks of ChatGLM3-6B and 19 blocks of LLaMA2-7B while attention Q/K/V layers remain uncompressed but INT4-quantized, the whole networks shrink by 1.94x and 1.60x. The deployed accelerator reaches first-token delays of 14.34ms and 15.20ms, which the paper reports as 1.45x and 1.57x reductions versus the same accelerator without TTD inference, with MLP speedups of 3.22x and 3.88x.

Load-bearing premise

The claimed 1.45x and 1.57x first-token delay reductions come from system emulation for the V80 platform rather than from measurements on a physical FPGA; if the emulated HBM/DDR bandwidth, AXI contention, or ping-pong buffer reordering is optimistic, the real speedups would be smaller.

Editorial extensions

If this is right

  • On the target FPGA, TTD inference is 3.22x and 3.88x faster in MLP evaluation and 2.19x and 1.78x faster per transformer block for ChatGLM3-6B and LLaMA2-7B, respectively.
  • Whole-network compression of 1.94x and 1.60x means both models deploy on a 32GB-HBM FPGA, so TTD can remove part of the weight-memory pressure that normally limits linear-layer accelerators.
  • The accuracy cost of the combined TTD plus INT4 pipeline is bounded: 4.21 C-Eval points for ChatGLM3-6B and 2.62 perplexity points for LLaMA2-7B on C4.
  • The same accelerator runs both transformer families by chaining only three operation types, TTD-linear, linear, and nonlinear, which suggests the mapping is portable across LLM architectures.
  • For both models the speed advantage over the no-TTD baseline persists across the decode phase with a KV cache, not just at the first token.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The ping-pong reordering trick is not specific to tensor-train: any decomposition that reshapes an intermediate tensor between contractions could hide its transpose or reshape in buffer addressing, so the same accelerator style may carry CP, Tucker, or mixed decompositions.
  • Because only attention Q/K/V and output layers were left uncompressed, and per-block compression ratios are 10.72x and 4.01x, applying the same pipeline to more blocks or to larger 13B/70B models is a plausible extension whose accuracy cost would need re-measuring.
  • A physical-silicon measurement is the natural next experiment: if HBM/DDR bandwidth and the ping-pong reorder behave as modeled, the claimed 1.45x/1.57x first-token gain should reproduce on real hardware and persist for long generations because of the KV cache.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

5 major / 5 minor

Summary. The paper proposes applying tensor-train decomposition (TTD) to selected linear layers of ChatGLM3-6B and LLaMA2-7B, and maps the resulting TT-core contractions onto an FPGA group-vector systolic array (GVSA) with FP16 x INT4 DSP-shared processing elements. Whole-network compression ratios of 1.94x and 1.60x are reported, with a C-Eval score decrease of 4.21 and a C4 perplexity increase of 2.62. Against the same accelerator without TTD, the authors report 1.45x and 1.57x first-token delay reductions. The TTD mathematics is standard, and the hardware mapping (ping-pong reordering, dataflow scheduling on GVSA, DSP packing) is described in detail. However, the headline LLaMA2-7B timing result is internally inconsistent: the per-block latencies in Table IV and Fig. 8, combined with the stated 19 compressed blocks, yield a first-token delay of about 17.76 ms rather than the reported 15.20 ms; the single-block and whole-network compression ratios likewise imply about 16 compressed blocks, not 19.

Significance. If the results are corrected and validated, the paper would make a useful contribution: it demonstrates an end-to-end path from TT-compressed LLM weights to a systolic-array implementation, with concrete mechanisms for reorder-free TTD inference and DSP sharing. The controlled comparison against the same GVSA without TTD is a legitimate way to isolate the effect of compression, and the resource and per-operation delay tables are informative. At present, the load-bearing LLaMA2-7B speedup and whole-network compression ratio are not internally consistent, and the absence of board-level measurements leaves the emulation-to-silicon mapping unverified. The results therefore must be treated as conditional until these points are resolved.

major comments (5)
  1. [V-B, Table IV, Fig. 8] Section V-B and Table IV report 19 TTD-compressed blocks out of 32 for LLaMA2-7B. Summing the per-operation delays in Table IV gives 413.46 us per TTD block; Fig. 8 gives 735.1 us for an uncompressed block; the output layer contributes 349.16 us. The first-token delay is therefore 19 x 413.46 + 13 x 735.1 + 349.16 = 17,761 us = 17.76 ms, not the reported 15.20 ms. The speedup against the approximately 23.87 ms baseline would be about 1.34x, not 1.57x. Please correct the table, the figure, or the stated block count, and recompute all downstream speedups.
  2. [V-B, Table I] Table I lists a single-block compression ratio of 4.01 for LLaMA2-7B and a whole-network compression ratio of 1.60. With 32 blocks and 19 compressed at CR 4.01 while 13 remain at CR 1, the whole-network CR is 32 / (19/4.01 + 13) = 1.80, not 1.60. The reported 1.60 corresponds to about 16 compressed blocks. The block count and the compression ratio must be reconciled.
  3. [V-A] The performance numbers are obtained from 'accelerator system emulation for V80' rather than from measurements on the physical FPGA, while the abstract and conclusion describe an FPGA implementation. The delay and speedup claims depend on how the emulation models HBM/DDR bandwidth, AXI contention, and the ping-pong buffer reordering between TTD stages. Please state explicitly which results are post-implementation timing reports and which are emulation, and provide validation or justification for the emulation timings, for example by comparing against a small on-board measurement or a known reference design.
  4. [V-A] The criterion for selecting which blocks to compress is not stated ('we choose specific blocks to perform TTD compression'). This choice directly determines the accuracy/speedup trade-off and is needed for reproducibility. Please specify the selection rule, such as a sensitivity analysis or a resource budget, and ideally report the sensitivity of accuracy and speedup to different block selections.
  5. [V-B] The accuracy results (C-Eval decrease of 4.21 and C4 perplexity increase of 2.62) are reported as single numbers with no variance, number of runs, or evaluation protocol details. Since these metrics are part of the paper's central claim, please report standard deviations or intervals and describe the evaluation setup (prompting, decoding parameters, dataset size).
minor comments (5)
  1. [V-A, Table II] The text says the AMD Alveo V80 has 12574K LUTs, while Table II lists 2574K LUTs as available; this appears to be a typo and should be corrected.
  2. [Table I] The definitions of 'CR for Linear Layer', 'CR for Single Block', and 'CR for Whole Network' are not given explicitly, and the role of INT4 quantization in these ratios is unclear. Please define each quantity and state whether quantization is included in the reported compression ratios.
  3. [Fig. 8] The bar values in Fig. 8 are difficult to read from the typeset text; providing the exact values in a table or in the caption would help verify the reported speedups.
  4. [III-A] The text refers to BatchNorm (BN) in the fused operators, but ChatGLM3-6B and LLaMA2-7B use LayerNorm rather than BatchNorm; please clarify the terminology.
  5. [Algorithm 1] The Factorization(N, d) function is not defined; the choice of tensorization shapes (n_k, m_k) in Table I appears ad hoc and should be explained or referenced.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: the TTD compression ratios and speedups are measured from design choices and a self-built baseline, not derived from the target results.

full rationale

The paper's central claims are not circular. The TTD compression ratios follow from Eq. (2) after the authors choose tensorization shapes and ranks; these are design parameters, not fitted to the reported first-token delay or speedup. The accuracy results (C-Eval decrease, PPL increase) are measured on a compressed network against the original, which is an external check. The speedup claims are obtained by comparing the proposed accelerator against a same-accelerator-without-TTD-inference baseline, a controlled comparison rather than a fitted prediction. The GVSA architecture [21] and DSP-sharing schemes [22]-[24] are cited as building blocks; they support the implementation but do not themselves assert the new speedup, and no load-bearing premise reduces to a self-citation. No equation in the paper is equivalent by construction to the reported speedups, and no parameter is renamed as a prediction. The internal arithmetic inconsistency in Table IV (19 TTD blocks at 413.5 us plus 13 uncompressed blocks at 735.1 us plus a 349.16 us output layer sums to about 17.76 ms, not the reported 15.20 ms) is a correctness and reproducibility concern, not a circularity, because the reported delay is presented as a measurement/emulation result rather than as a derived consequence of the compression equations.

Assumptions & free parameters 4 free parameters · 4 assumptions · 0 invented entities

The central claims rest on four design choices (rank, tensorization shapes, block selection, GVSA parallelism) plus domain assumptions about DSP arithmetic accuracy and emulation fidelity. No new physical entities are introduced. The accuracy and performance claims depend on unverified assumptions that are not covered by independent evidence in the paper.

free parameters (4)
  • TTD rank r = 16
    Set to 16 for all compressed linear layers; directly controls the CR (Eq. 2) and model accuracy. No rank search or Pareto analysis is reported, and all results use this single value.
  • Per-layer tensorization shapes (n_k, m_k) = As in Table I, e.g., LinearO [16,8,8,4] vs [4,8,8,16]
    The factorization of N and M into d dimensions is chosen per layer without a stated optimization procedure, and it affects both CR and the TTD inference dataflow.
  • TTD compressed block count = 15 blocks for ChatGLM3-6B, 19 for LLaMA2-7B
    The paper says 'specific blocks' are chosen but gives no criterion; this selection influences whole-network CR and the measured speedup.
  • GVSA parallelism (Tin, Tout, Tn) = 128, 32, 16
    Hardware parallelism parameters chosen by the designer; they shape resource usage and latency numbers in Section V.
assumptions (4)
  • standard math SVD-based TTD yields a valid low-rank approximation of the weight tensor
    Used in Algorithm 1 following Oseledets [14]; no proof or error bound is repeated.
  • domain assumption The FP16 x INT4 DSP-shared multiplier computes MACs with sufficient accuracy for inference
    Described in Section IV and Fig. 7; no numerical error analysis is provided, but the reported PPL/C-Eval results depend on this assumption.
  • domain assumption Vivado synthesis and system emulation on V80 are representative of real FPGA performance
    Section V-A reports 'accelerator system emulation for V80'; no on-board measurement is given, yet all delay and speedup tables rely on emulation.
  • domain assumption Operator fusion and chaining preserve the original model's semantics
    Section III-A assumes fused BN/Res/LN and TTD operations behave identically to unfused blocks; no intermediate tensor verification is shown.

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Cite this review

Pith. "Pith review of A Tensor-Train Decomposition based Compression of LLMs on Group Vector Systolic Accelerator." pith.science (2026). https://pith.science/paper/EJF5JN4V

@misc{pith2026250119135,
  author       = {Pith},
  title        = {Pith review of: A Tensor-Train Decomposition based Compression of LLMs on Group Vector Systolic Accelerator},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/EJF5JN4V}},
  note         = {Machine review of arXiv:2501.19135}
}
abstract

Large language models (LLMs) are both storage-intensive and computation-intensive, posing significant challenges when deployed on resource-constrained hardware. As linear layers in LLMs are mainly resource consuming parts, this paper develops a tensor-train decomposition (TTD) for LLMs with a further hardware implementation on FPGA. TTD compression is applied to the linear layers in ChatGLM3-6B and LLaMA2-7B models with compression ratios (CRs) for the whole network 1.94$\times$ and 1.60$\times$, respectively. The compressed LLMs are further implemented on FPGA hardware within a highly efficient group vector systolic array (GVSA) architecture, which has DSP-shared parallel vector PEs for TTD inference, as well as optimized data communication in the accelerator. Experimental results show that the corresponding TTD based LLM accelerator implemented on FPGA achieves 1.45$\times$ and 1.57$\times$ reduction in first token delay for ChatGLM3-6B and LLaMA2-7B models, respectively.

Figures

Figures reproduced from arXiv: 2501.19135 by the authors.

Figure 1
Figure 1. LLMs with TTD compressed linear layers mapping on FPGA [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. Architecture of ChatGLM3-6B and LLaMA2-7B. [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 3
Figure 3. Basic principles of tensorization and TTD (Example with [PITH_FULL_IMAGE:figures/full_fig_p002_3.png] view at source ↗
Figures from the paper (6 more)
Figure 4
Figure 4. Figure 4: Operator execution order for inference of TTD compressed LLMs. [PITH_FULL_IMAGE:figures/full_fig_p003_4.png]
Figure 5
Figure 5. Figure 5: Architecture of GVSA when Tn = Tout/2 [PITH_FULL_IMAGE:figures/full_fig_p003_5.png]
Figure 6
Figure 6. Figure 6: (a) Data mapping of cores; (b) Data mapping of input features; (c) [PITH_FULL_IMAGE:figures/full_fig_p004_6.png]
Figure 7
Figure 7. Figure 7: (a)DSP-shared GVSA vector PEs; (b)According design by DSP in [PITH_FULL_IMAGE:figures/full_fig_p005_7.png]
Figure 8
Figure 8. Figure 8: Performance comparison with accelerator without TTD inference on [PITH_FULL_IMAGE:figures/full_fig_p006_8.png]
Figure 9
Figure 9. Figure 9: (a) Speed comparison with accelerator without TTD inference at [PITH_FULL_IMAGE:figures/full_fig_p006_9.png]

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