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arxiv: 2502.20415 · v4 · pith:ICPKRJ4Nnew · submitted 2025-02-23 · 💻 cs.AR · cs.NE

A Quarter of a Century of Neuromorphic Architectures on FPGAs -- an Overview

Wiktor J. Szczerek , Artur Podobas This is my paper

Pith reviewed 2026-05-23 02:24 UTC · model grok-4.3

classification 💻 cs.AR cs.NE
keywords neuromorphic computingFPGAspiking neural networksdigital architecturestaxonomyhardware implementationtrends
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The pith

A taxonomy of FPGA neuromorphic architectures organizes designs by shared features and reveals long-term trends.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper surveys twenty-five years of digital neuromorphic architectures implemented on field-programmable gate arrays. It constructs a taxonomy that sorts these architectures into groups based on distinct architectural features. The taxonomy also records the advantages and disadvantages associated with each group. From this classification the authors extract observable trends and make predictions about the future evolution of such systems. Researchers can use the resulting map to navigate design decisions when building hardware models of spiking neural networks.

Core claim

The central claim is that the literature on digital NMAs on FPGAs can be usefully organized into a taxonomy based on groups of distinct architectural features, with each group having identifiable advantages and disadvantages, and that this organization reveals clear trends and allows for predictions about future architectures.

What carries the argument

The taxonomy of neuromorphic architectures (NMAs) on FPGAs, which classifies designs according to groups of distinct architectural features and evaluates their trade-offs.

If this is right

  • Future neuromorphic designs can draw on the documented advantages and disadvantages when selecting architectural features.
  • Identified trends provide a basis for anticipating the direction of hardware implementations of spiking networks.
  • Researchers gain a structured set of references for common design choices in FPGA-based NMAs.
  • Predictions derived from the taxonomy can be validated or refined as new architectures appear.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The taxonomy could serve as a foundation for creating standardized benchmarks across different architectural families.
  • Mapping real-world application performance onto the taxonomy groups might reveal which features best suit particular tasks.
  • Updates to the taxonomy as new papers appear could track the field's evolution in real time.

Load-bearing premise

The papers examined in the review form a representative sample of the entire body of work on digital neuromorphic architectures on FPGAs over the past twenty-five years.

What would settle it

A systematic search that uncovers a substantial body of FPGA neuromorphic designs whose architectural features fall outside all the groups defined in the taxonomy.

Figures

Figures reproduced from arXiv: 2502.20415 by Artur Podobas, Wiktor J. Szczerek.

Figure 1
Figure 1. Figure 1: Abstract view of an FPGA, showing reconfigurable logic (blue), DSP-blocks (green), BRAM (red), and hardened memory controller and processor blocks. Illustration based on [12]. 2 BACKGROUND In the following section, we present the key concepts related to this survey: (i)the Field-Programmable Gate Arrays (FPGAs), (ii) Neuromorphic Architectures (NMAs) and (iii) Spiking Neural Networks (SNNs). Furthermore, w… view at source ↗
Figure 2
Figure 2. Figure 2: Proposed taxonomy - classes [PITH_FULL_IMAGE:figures/full_fig_p006_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Simplified diagram of a Class 0 NMA. possess 2 or all of them. Every subsection consists of a small introduction listing the features common for the appropriate Class an summaries of the surveyed architectures showing key design decisions that distinguish them from other architectures. The aforementioned subsections are divided into paragraphs for three time periods: (i) early implementations (1998–2009), … view at source ↗
Figure 4
Figure 4. Figure 4: Simplified diagram of a Class 1 NMA. neuron models. The models utilized floating-point arithmetic, and exponential functions were implemented as LUTs. The system was using a MicroBlaze processor for configuration and supervision, as well as communication between subunits. The entire system operated at 100 MHz and allowed the simulation of six different configurations of soma, dendrite and synapse types fro… view at source ↗
Figure 5
Figure 5. Figure 5: Simplified diagram of a Class 2 NMA. potential use case for this architecture - implementation of a set of CPGs. Wang et al. (2013) [91] presented an NMA realizing a concept of a polychronous network (SNN where the axonal delays are used to store information instead of weights). The architecture used two arrays of PEs - one for the neurons and one for the axons - sharing two AER-based buses. The former (12… view at source ↗
Figure 6
Figure 6. Figure 6: Simplified diagram of a Class 3 NMA. MHz. Neil et al. (2014) [133] presented Minitaur - an SNN accelerator designed for image inference and robotics applications4 . The architecture comprised 32 PEs with bespoke state and weight information caches. The neuron model was LIF with a decay rate based on the distance in time between the consecutive events. The system used broadcasting, instead of point-to-point… view at source ↗
Figure 7
Figure 7. Figure 7: Simplified diagram of a Class 4 NMA. clocked at 200 MHz, with processing speed of 161 frames per second. Li et al. (2021) [137] presented an NMA with a clock/event-driven hybrid update scheme - however, according to the Features described in Section 2.3, the system is a member of Class 3. It comprised 12 PEs with five computational cores (CC) in every PE, supporting CUBA LIF neurons with STDP-based learnin… view at source ↗
Figure 8
Figure 8. Figure 8: Simplified diagram of a Class 5 NMA. auditory data were passed through the layers, and the results from all the layers were transferred to the centralised Bayesian classifier module. The synapses realized the spike traces with exponential kernels. The design was multiplierless, utilizing bit shifts and adders. The authors conducted tests on the system with speech samples consisting of spoken digits with ap… view at source ↗
Figure 9
Figure 9. Figure 9: Simplified diagram of a Class 6 NMA. 3.6 Class 5 (Traits: fully parallel, asynchronous network update) Class 5 architectures support two Traits: fully parallel operation and asynchronous network update. Because the necessary data is stored off-chip, they can support large SNNs and can potentially achieve high operation speeds, due to fully parallel operation and updating the neuron states only if there are… view at source ↗
Figure 10
Figure 10. Figure 10: Simplified diagram of a Class 7 NMA. 3.8 Class 7 (Traits: fully parallel, collocated computation and memory, asynchronous network update) Class 7 architectures support all three Traits, and their operation can be deemed the most brain-like. They are also the most bound by the on-chip resources out of all of the Classes, but can allow for the fastest and most energy-efficient operation. However, realizing … view at source ↗
Figure 11
Figure 11. Figure 11: Class population structure through years. 1998 2000 2003 2004 2005 2006 2007 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 0 2 4 6 8 10 12 14 16 18 20 Year Number of implementations IF LIF IZH HH FHN SRM SRM0 AdEx DSSN MBED PULSED [PITH_FULL_IMAGE:figures/full_fig_p025_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: Share of different neuron models through years. 25/39 [PITH_FULL_IMAGE:figures/full_fig_p025_12.png] view at source ↗
Figure 13
Figure 13. Figure 13: Complexity of the implemented architectures. classification task neuroscience NN research image processing robotics mathematics NN-based memory NN optimization path planning 41% 28% 14% 7% 4% 3% 2% <1% <1% [PITH_FULL_IMAGE:figures/full_fig_p026_13.png] view at source ↗
Figure 14
Figure 14. Figure 14: Share of use cases for the surveyed architectures. 26/39 [PITH_FULL_IMAGE:figures/full_fig_p026_14.png] view at source ↗
Figure 15
Figure 15. Figure 15: Predicted LB number required to implement 1011 of neurons on an FPGA by Class. 5 CONCLUSION The FPGA-based neuromorphic systems can be implemented in various ways, with different advantages and disadvantages, which is reflected by the Classes of the Taxonomy we provided. Representatives of those Classes fit diverse sets of requirements and allow for achieving diverse goals - from classification tasks to n… view at source ↗
read the original abstract

Neuromorphic computing is a relatively new discipline of computer science, where the principles of biological brain's computation and memory are used to create a new way of processing information, based on networks of spiking neurons. Those networks can be implemented as both analog and digital implementations, where for the latter, the Field Programmable Gate Arrays (FPGAs) are a frequent choice, due to their inherent flexibility, allowing the researchers to easily design hardware neuromorphic architecture (NMAs). Moreover, digital NMAs show good promise in simulating various spiking neural networks because of their inherent accuracy and resilience to noise, as opposed to analog implementations. This paper presents an overview of digital NMAs implemented on FPGAs, with a goal of providing useful references to various architectural design choices to the researchers interested in digital neuromorphic systems. We present a taxonomy of NMAs that highlights groups of distinct architectural features, their advantages and disadvantages and identify trends and predictions for the future of those architectures.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The paper provides an overview of digital neuromorphic architectures (NMAs) implemented on FPGAs over the past 25 years. It aims to deliver a taxonomy grouping distinct architectural features, discuss their advantages and disadvantages, and identify trends and future predictions to serve as a reference for researchers designing digital neuromorphic systems.

Significance. If the taxonomy is reproducible and the reviewed corpus representative, the work could offer a useful organizing framework for FPGA-based spiking neural network implementations, highlighting design trade-offs in a field where hardware flexibility is key. The descriptive nature means impact depends on the completeness and rigor of the literature synthesis rather than novel derivations or proofs.

major comments (2)
  1. [Abstract and introduction (implied methodology section)] The central taxonomy and trend-identification claims rest on an unspecified literature corpus. No search protocol, database list, inclusion/exclusion criteria, total paper count, or year-by-year distribution is provided, making it impossible to assess whether the reviewed body is representative across the 25-year span or whether classification boundaries are reproducible. This directly undermines the reliability of the advantage/disadvantage summaries and the identified trends.
  2. [Taxonomy presentation (section describing the taxonomy)] Classification decisions lack any inter-rater reliability measure, sensitivity analysis to alternative groupings, or explicit decision rules. Without these, the taxonomy risks being author-specific rather than a stable organizing structure, which is load-bearing for the paper's stated goal of highlighting groups of distinct architectural features.
minor comments (1)
  1. [Abstract] Clarify the exact scope (e.g., only digital implementations, exclusion of analog or mixed-signal FPGA work) early in the manuscript to set reader expectations.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive comments on our survey paper. The points raised about methodology transparency and taxonomy reproducibility are valid and will be addressed through revisions to strengthen the manuscript.

read point-by-point responses

  1. Referee: [Abstract and introduction (implied methodology section)] The central taxonomy and trend-identification claims rest on an unspecified literature corpus. No search protocol, database list, inclusion/exclusion criteria, total paper count, or year-by-year distribution is provided, making it impossible to assess whether the reviewed body is representative across the 25-year span or whether classification boundaries are reproducible. This directly undermines the reliability of the advantage/disadvantage summaries and the identified trends.

    Authors: We agree that the current manuscript lacks an explicit description of the literature selection process. In the revised version, we will add a dedicated 'Literature Selection and Review Methodology' subsection. It will detail the databases used (IEEE Xplore, ACM Digital Library, Google Scholar), search terms (combinations of 'neuromorphic FPGA', 'spiking neural network hardware', 'digital neuromorphic architecture'), time span (1999-2024), inclusion criteria (peer-reviewed works on digital FPGA-based NMAs), exclusion criteria (analog implementations, non-FPGA platforms, non-spiking networks), the total number of papers reviewed, and a year-by-year distribution. This will enable readers to evaluate corpus representativeness. revision: yes

  2. Referee: [Taxonomy presentation (section describing the taxonomy)] Classification decisions lack any inter-rater reliability measure, sensitivity analysis to alternative groupings, or explicit decision rules. Without these, the taxonomy risks being author-specific rather than a stable organizing structure, which is load-bearing for the paper's stated goal of highlighting groups of distinct architectural features.

    Authors: We will revise the taxonomy section to include explicit decision rules for category assignment, based on observable features such as neuron model (e.g., LIF vs. Izhikevich), synaptic connectivity approach, parallelism level, and memory organization. We will also describe the iterative development process used by the authors. Inter-rater reliability metrics are not directly applicable to a single-team taxonomy construction; instead, we will discuss alternative groupings considered during development and the rationale for the final structure to address sensitivity concerns. revision: partial

Circularity Check

0 steps flagged

No circularity: descriptive literature review with no derivations or self-referential reductions

full rationale

The manuscript is a survey paper that compiles and taxonomizes existing FPGA-based neuromorphic architectures from the literature. It contains no equations, fitted parameters, model predictions, or uniqueness theorems. The taxonomy and trend identification are presented as author-constructed classifications of reviewed works rather than outputs derived from the paper's own inputs. No self-citation chains are load-bearing for any central claim, and no step reduces by construction to a prior definition or fit within the paper. This is the expected outcome for a non-derivational overview.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

This is a literature review with no new mathematical claims, derivations, or postulated entities.

pith-pipeline@v0.9.0 · 5698 in / 1008 out tokens · 34687 ms · 2026-05-23T02:24:19.394741+00:00 · methodology

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Cited by 1 Pith paper

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score.

  1. NeuroRing: Scaling Spiking Neural Networks via Multi-FPGA Bidirectional Ring Topologies and Stream-Dataflow Architectures

    cs.AR 2026-04 unverdicted novelty 5.0

    NeuroRing delivers a modular multi-FPGA accelerator for spiking neural networks that achieves real-time factor 0.83 on the full cortical microcircuit while preserving NEST activity statistics and showing scaling behavior.

Reference graph

Works this paper leans on

232 extracted references · 232 canonical work pages · cited by 1 Pith paper · 1 internal anchor

  1. [1]

    Moore’s law: past, present and future,

    R. R. Schaller, “Moore’s law: past, present and future,”IEEE spectrum, vol. 34, no. 6, pp. 52–59, 1997

    work page 1997

  2. [2]

    A 30 year retrospective on Dennard’s MOSFET scaling paper,

    M. Bohr, “A 30 year retrospective on Dennard’s MOSFET scaling paper,”IEEE Solid-State Circuits Society Newsletter, vol. 12, no. 1, pp. 11–13, 2007

    work page 2007

  3. [3]

    A perspective on today’s scaling challenges and possible future directions,

    R. H. Dennard, J. Cai, and A. Kumar, “A perspective on today’s scaling challenges and possible future directions,” inHandbook of thin film deposition, pp. 3–18, Elsevier, 2018

    work page 2018

  4. [4]

    Dark silicon and the end of multicore scaling,

    H. Esmaeilzadeh, E. Blem, R. St. Amant, K. Sankaralingam, and D. Burger, “Dark silicon and the end of multicore scaling,” inProceedings of the 38th annual international symposium on Computer architecture, pp. 365–376, 2011

    work page 2011

  5. [5]

    The future of computing beyond Moore’s Law,

    J. Shalf, “The future of computing beyond Moore’s Law,”Philosophical Transactions of the Royal Society A, vol. 378, no. 2166, p. 20190061, 2020

    work page 2020

  6. [6]

    There’s plenty of room at the Top: What will drive computer performance after Moore’s law?,

    C. E. Leiserson, N. C. Thompson, J. S. Emer, B. C. Kuszmaul, B. W. Lampson, D. Sanchez, and T. B. Schardl, “There’s plenty of room at the Top: What will drive computer performance after Moore’s law?,”Science, vol. 368, no. 6495, p. eaam9744, 2020. 27/39

    work page 2020

  7. [7]

    A survey on quantum computing technology,

    L. Gyongyosi and S. Imre, “A survey on quantum computing technology,” Computer Science Review, vol. 31, pp. 51–71, 2019

    work page 2019

  8. [8]

    A survey on adiabatic logic families for implementing reversible logic circuits,

    R. Bommi and R. S. Selvakumar, “A survey on adiabatic logic families for implementing reversible logic circuits,” in2018 IEEE international conference on computational intelligence and computing research (ICCIC), pp. 1–4, IEEE, 2018

    work page 2018

  9. [9]

    A review of analog computing,

    B. J. MacLennan, “A review of analog computing,”Department of Electrical Engineering & Com- puter Science, University of Tennessee, Technical Report UT-CS-07-601 (September), pp. 19798– 19807, 2007

    work page 2007

  10. [10]

    A Survey of Neuromorphic Computing and Neural Networks in Hardware

    C. D. Schuman, T. E. Potok, R. M. Patton, J. D. Birdwell, M. E. Dean, G. S. Rose, and J. S. Plank, “A survey of neuromorphic computing and neural networks in hardware,”arXiv preprint arXiv:1705.06963, 2017

    work page internal anchor Pith review Pith/arXiv arXiv 2017

  11. [11]

    A survey on coarse-grained reconfigurable architectures from a performance perspective,

    A. Podobas, K. Sano, and S. Matsuoka, “A survey on coarse-grained reconfigurable architectures from a performance perspective,” IEEE access : practical innovations, open solutions , vol. 8, pp. 146719–146743, 2020

    work page 2020

  12. [12]

    FPGA architecture: Survey and challenges,

    I. Kuon, R. Tessier, J. Rose, and others, “FPGA architecture: Survey and challenges,”Foundations and Trends® in Electronic Design Automation, vol. 2, no. 2, pp. 135–253, 2008

    work page 2008

  13. [13]

    Neuromorphic electronic systems,

    C. Mead, “Neuromorphic electronic systems,”Proceedings of the IEEE, vol. 78, no. 10, pp. 1629– 1636, 1990

    work page 1990

  14. [14]

    Loihi: A neuromorphic manycore processor with on-chip learning,

    M. Davies, N. Srinivasa, T.-H. Lin, G. Chinya, Y . Cao, S. H. Choday, G. Dimou, P. Joshi, N. Imam, S. Jain, and others, “Loihi: A neuromorphic manycore processor with on-chip learning,” Ieee Micro, vol. 38, no. 1, pp. 82–99, 2018

    work page 2018

  15. [15]

    Truenorth: Design and tool flow of a 65 mw 1 million neuron programmable neurosynaptic chip,

    F. Akopyan, J. Sawada, A. Cassidy, R. Alvarez-Icaza, J. Arthur, P. Merolla, N. Imam, Y . Nakamura, P. Datta, G.-J. Nam, and others, “Truenorth: Design and tool flow of a 65 mw 1 million neuron programmable neurosynaptic chip,” IEEE transactions on computer-aided design of integrated circuits and systems, vol. 34, no. 10, pp. 1537–1557, 2015

    work page 2015

  16. [16]

    Braindrop: A mixed-signal neuromorphic architecture with a dynamical systems-based programming model,

    A. Neckar, S. Fok, B. V . Benjamin, T. C. Stewart, N. N. Oza, A. R. V oelker, C. Eliasmith, R. Manohar, and K. Boahen, “Braindrop: A mixed-signal neuromorphic architecture with a dynamical systems-based programming model,” Proceedings of the IEEE, vol. 107, no. 1, pp. 144– 164, 2018

    work page 2018

  17. [17]

    Neuromorphic silicon neuron circuits,

    G. Indiveri, B. Linares-Barranco, T. J. Hamilton, A. v. Schaik, R. Etienne-Cummings, T. Delbruck, S.-C. Liu, P. Dudek, P. H¨afliger, S. Renaud, and others, “Neuromorphic silicon neuron circuits,” Frontiers in neuroscience, vol. 5, p. 73, 2011

    work page 2011

  18. [18]

    Review of memristor devices in neuromorphic computing: materials sciences and device challenges,

    Y . Li, Z. Wang, R. Midya, Q. Xia, and J. J. Yang, “Review of memristor devices in neuromorphic computing: materials sciences and device challenges,” Journal of Physics D: Applied Physics , vol. 51, no. 50, p. 503002, 2018

    work page 2018

  19. [19]

    Photonics for artificial intelligence and neuromorphic computing,

    B. J. Shastri, A. N. Tait, T. Ferreira de Lima, W. H. Pernice, H. Bhaskaran, C. D. Wright, and P. R. Prucnal, “Photonics for artificial intelligence and neuromorphic computing,” Nature Photonics, vol. 15, no. 2, pp. 102–114, 2021

    work page 2021

  20. [20]

    Networks of spiking neurons: the third generation of neural network models,

    W. Maass, “Networks of spiking neurons: the third generation of neural network models,”Neural networks, vol. 10, no. 9, pp. 1659–1671, 1997

    work page 1997

  21. [21]

    Advancing neuromorphic computing with loihi: A survey of results and outlook,

    M. Davies, A. Wild, G. Orchard, Y . Sandamirskaya, G. A. F. Guerra, P. Joshi, P. Plank, and S. R. Risbud, “Advancing neuromorphic computing with loihi: A survey of results and outlook,” Proceedings of the IEEE, vol. 109, no. 5, pp. 911–934, 2021

    work page 2021

  22. [22]

    Can dataflow subsume von Neumann computing?,

    R. S. Nikhil, “Can dataflow subsume von Neumann computing?,” inProceedings of the 16th annual international symposium on Computer architecture, pp. 262–272, 1989

    work page 1989

  23. [23]

    Competitive Hebbian learning through spike-timing- dependent synaptic plasticity,

    S. Song, K. D. Miller, and L. F. Abbott, “Competitive Hebbian learning through spike-timing- dependent synaptic plasticity,”Nature neuroscience, vol. 3, no. 9, pp. 919–926, 2000

    work page 2000

  24. [24]

    Unsupervised representation learning with Heb- bian synaptic and structural plasticity in brain-like feedforward neural networks,

    N. Ravichandran, A. Lansner, and P. Herman, “Unsupervised representation learning with Heb- bian synaptic and structural plasticity in brain-like feedforward neural networks,”arXiv preprint arXiv:2406.04733, 2024

    work page arXiv 2024

  25. [25]

    A solution to the learning dilemma for recurrent networks of spiking neurons,

    G. Bellec, F. Scherr, A. Subramoney, E. Hajek, D. Salaj, R. Legenstein, and W. Maass, “A solution to the learning dilemma for recurrent networks of spiking neurons,” Nature communications, vol. 11, no. 1, p. 3625, 2020

    work page 2020

  26. [26]

    Survey on FPGA architecture and recent applications,

    S. Gandhare and B. Karthikeyan, “Survey on FPGA architecture and recent applications,” in2019 international conference on vision towards emerging trends in communication and networking 28/39 (ViTECoN), pp. 1–4, IEEE, 2019

    work page 2019

  27. [27]

    Juan Jose Rodriguez Andina, E. D. l. T. Arnanz, and M. D. V . Pe{\˜n}a, FPGAs: fundamentals, advanced features, and applications in industrial electronics. CRC Press, 2017

    work page 2017

  28. [28]

    Reconfigurable fault tolerance: A comprehensive framework for reliable and adaptive FPGA-based space computing,

    A. Jacobs, G. Cieslewski, A. D. George, A. Gordon-Ross, and H. Lam, “Reconfigurable fault tolerance: A comprehensive framework for reliable and adaptive FPGA-based space computing,” ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 5, no. 4, pp. 1–30, 2012

    work page 2012

  29. [29]

    Enabling FPGAs in hyperscale data centers,

    J. Weerasinghe, F. Abel, C. Hagleitner, and A. Herkersdorf, “Enabling FPGAs in hyperscale data centers,” in2015 IEEE 12th intl conf on ubiquitous intelligence and computing and 2015 IEEE 12th intl conf on autonomic and trusted computing and 2015 IEEE 15th intl conf on scalable computing and communications and its associated workshops (UIC-ATC-ScalCom), pp...

    work page 2015

  30. [30]

    Soft core processors and embedded processing: a survey and analysis,

    H. Calder´on, C. Elena, and S. Vassiliadis, “Soft core processors and embedded processing: a survey and analysis,” inProceedings of-ProRISC, pp. 483–488, 2005

    work page 2005

  31. [31]

    FlexGrip: a soft GPGPU for fpgas,

    K. Andryc, M. Merchant, and R. Tessier, “FlexGrip: a soft GPGPU for fpgas,” in2013 international conference on field-programmable technology (FPT), pp. 230–237, IEEE, 2013

    work page 2013

  32. [32]

    Designing and accelerating spiking neural networks using OpenCL for FPGAs,

    A. Podobas and S. Matsuoka, “Designing and accelerating spiking neural networks using OpenCL for FPGAs,” in2017 international conference on field programmable technology (ICFPT), pp. 255– 258, IEEE, 2017

    work page 2017

  33. [33]

    An FPGA implementation of deep spiking neural networks for low-power and fast classification,

    X. Ju, B. Fang, R. Yan, X. Xu, and H. Tang, “An FPGA implementation of deep spiking neural networks for low-power and fast classification,”Neural computation, vol. 32, no. 1, pp. 182–204, 2020

    work page 2020

  34. [34]

    Fast algorithms for spiking neural network simulation with fpgas,

    B. A. Lindqvist and A. Podobas, “Fast algorithms for spiking neural network simulation with fpgas,”arXiv preprint arXiv:2405.02019, 2024

    work page arXiv 2024

  35. [35]

    A survey on neuromorphic computing: Models and hardware,

    A. Shrestha, H. Fang, Z. Mei, D. P. Rider, Q. Wu, and Q. Qiu, “A survey on neuromorphic computing: Models and hardware,” IEEE Circuits and Systems Magazine, vol. 22, no. 2, pp. 6–35, 2022

    work page 2022

  36. [36]

    A survey of FPGA implementations of artificial spiking neurons models,

    M. Ma´slanka and M. Gorgo´n, “A survey of FPGA implementations of artificial spiking neurons models,”Bio-Algorithms and Med-Systems, vol. 8, no. 1, p. 77, 2012

    work page 2012

  37. [37]

    FPGA-based spiking neural networks,

    A. Mehrabi and A. van Schaik, “FPGA-based spiking neural networks,” 2024

    work page 2024

  38. [38]

    Challenges for large-scale implementations of spiking neural networks on FPGAs,

    L. P. Maguire, T. M. McGinnity, B. Glackin, A. Ghani, A. Belatreche, and J. Harkin, “Challenges for large-scale implementations of spiking neural networks on FPGAs,”Neurocomputing, vol. 71, no. 1-3, pp. 13–29, 2007

    work page 2007

  39. [39]

    Evaluating high-level design strategies on FPGAs for high-performance computing,

    A. Podobas, H. R. Zohouri, N. Maruyama, and S. Matsuoka, “Evaluating high-level design strategies on FPGAs for high-performance computing,” in2017 27th international conference on field programmable logic and applications (FPL), pp. 1–4, IEEE, 2017

    work page 2017

  40. [40]

    Evaluating and optimizing OpenCL kernels for high performance computing with FPGAs,

    H. R. Zohouri, N. Maruyama, A. Smith, M. Matsuda, and S. Matsuoka, “Evaluating and optimizing OpenCL kernels for high performance computing with FPGAs,” in SC’16: Proceedings of the international conference for high performance computing, networking, storage and analysis , pp. 409–420, IEEE, 2016

    work page 2016

  41. [41]

    A survey and evaluation of FPGA high-level synthesis tools,

    R. Nane, V .-M. Sima, C. Pilato, J. Choi, B. Fort, A. Canis, Y . T. Chen, H. Hsiao, S. Brown, F. Ferrandi, and others, “A survey and evaluation of FPGA high-level synthesis tools,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , vol. 35, no. 10, pp. 1591–1604, 2015

    work page 2015

  42. [42]

    The cell-type specific cortical microcircuit: relating structure and activity in a full-scale spiking network model,

    T. C. Potjans and M. Diesmann, “The cell-type specific cortical microcircuit: relating structure and activity in a full-scale spiking network model,”Cerebral cortex, vol. 24, no. 3, pp. 785–806, 2014

    work page 2014

  43. [43]

    The NEURON simulation environment,

    M. L. Hines and N. T. Carnevale, “The NEURON simulation environment,”Neural computation, vol. 9, no. 6, pp. 1179–1209, 1997

    work page 1997

  44. [44]

    Nest (neural simulation tool),

    M.-O. Gewaltig and M. Diesmann, “Nest (neural simulation tool),” Scholarpedia, vol. 2, no. 4, p. 1430, 2007

    work page 2007

  45. [45]

    Brian 2, an intuitive and efficient neural simulator,

    M. Stimberg, R. Brette, and D. F. Goodman, “Brian 2, an intuitive and efficient neural simulator,” elife, vol. 8, p. e47314, 2019

    work page 2019

  46. [46]

    Liquid state machines: motivation, theory, and applications,

    W. Maass, “Liquid state machines: motivation, theory, and applications,”Computability in context: computation and logic in the real world, pp. 275–296, 2011. Publisher: World Scientific

    work page 2011

  47. [47]

    The central nervous control of flight in a locust,

    D. M. Wilson, “The central nervous control of flight in a locust,”Journal of Experimental Biology, 29/39 vol. 38, no. 2, pp. 471–490, 1961. Publisher: The Company of Biologists Ltd

    work page 1961

  48. [48]

    An electrophysiological demonstration of the axonal projections of single spinal interneurones in the cat,

    E. Jankowska and W. Roberts, “An electrophysiological demonstration of the axonal projections of single spinal interneurones in the cat,” The Journal of Physiology, vol. 222, no. 3, pp. 597–622,

    work page

  49. [49]

    Publisher: Wiley Online Library

    work page

  50. [50]

    Mahowald, An analog VLSI system for stereoscopic vision , vol

    M. Mahowald, An analog VLSI system for stereoscopic vision , vol. 265. Springer Science & Business Media, 1994

    work page 1994

  51. [51]

    Which model to use for cortical spiking neurons?,

    E. M. Izhikevich, “Which model to use for cortical spiking neurons?,”IEEE transactions on neural networks, vol. 15, no. 5, pp. 1063–1070, 2004

    work page 2004

  52. [52]

    OpenWorm: overview and recent advances in integrative biological simulation of Caenorhabditis elegans,

    G. P. Sarma, C. W. Lee, T. Portegys, V . Ghayoomie, T. Jacobs, B. Alicea, M. Cantarelli, M. Currie, R. C. Gerkin, S. Gingell, and others, “OpenWorm: overview and recent advances in integrative biological simulation of Caenorhabditis elegans,”Philosophical Transactions of the Royal Society B, vol. 373, no. 1758, p. 20170382, 2018

    work page 2018

  53. [53]

    Unsupervised learning of digit recognition using spike-timing-dependent plasticity,

    P. U. Diehl and M. Cook, “Unsupervised learning of digit recognition using spike-timing-dependent plasticity,”Frontiers in computational neuroscience, vol. 9, p. 99, 2015

    work page 2015

  54. [54]

    A quantitative description of membrane current and its application to conduction and excitation in nerve,

    A. L. Hodgkin and A. F. Huxley, “A quantitative description of membrane current and its application to conduction and excitation in nerve,”The Journal of physiology, vol. 117, no. 4, p. 500, 1952

    work page 1952

  55. [55]

    Gerstner, W

    W. Gerstner, W. M. Kistler, R. Naud, and L. Paninski,Neuronal dynamics: From single neurons to networks and models of cognition. Cambridge University Press, 2014

    work page 2014

  56. [56]

    Pulse coupled neural network implementation in FPGA,

    J. T. A. Waldemark, T. Lindblad, C. S. Lindsey, K. E. Waldemark, J. ¨Oberg, and M. Millberg, “Pulse coupled neural network implementation in FPGA,” vol. 3390, pp. 392–402, SPIE, 1998

    work page 1998

  57. [57]

    E. T. Claverol, An event-driven approach to biologically realistic simulation of neural aggregates. PhD Thesis, University of Southampton, 2000

    work page 2000

  58. [58]

    A model of a CA3 hippocampal pyramidal neuron incorporating voltage-clamp data on intrinsic conductances,

    R. D. Traub, R. K. Wong, R. Miles, and H. Michelson, “A model of a CA3 hippocampal pyramidal neuron incorporating voltage-clamp data on intrinsic conductances,”Journal of neurophysiology, vol. 66, no. 2, pp. 635–650, 1991

    work page 1991

  59. [59]

    Equal numbers of neuronal and nonneuronal cells make the human brain an isometrically scaled-up primate brain,

    F. A. Azevedo, L. R. Carvalho, L. T. Grinberg, J. M. Farfel, R. E. Ferretti, R. E. Leite, W. J. Filho, R. Lent, and S. Herculano-Houzel, “Equal numbers of neuronal and nonneuronal cells make the human brain an isometrically scaled-up primate brain,” Journal of Comparative Neurology, vol. 513, no. 5, pp. 532–541, 2009. Publisher: Wiley Online Library

    work page 2009

  60. [60]

    GABAA, NMDA and AMPA receptors: a developmentally regulatedmenage a trois’,

    Y . Ben-Ari, R. Khazipov, X. Leinekugel, O. Caillard, and J.-L. Gaiarsa, “GABAA, NMDA and AMPA receptors: a developmentally regulatedmenage a trois’,”Trends in neurosciences, vol. 20, no. 11, pp. 523–529, 1997

    work page 1997

  61. [61]

    Synaptic plasticity: multiple forms, functions, and mechanisms,

    A. Citri and R. C. Malenka, “Synaptic plasticity: multiple forms, functions, and mechanisms,” Neuropsychopharmacology : official publication of the American College of Neuropsychopharma- cology, vol. 33, no. 1, pp. 18–41, 2008

    work page 2008

  62. [62]

    Hebbian learning and plasticity,

    W. Gerstner, “Hebbian learning and plasticity,” From neuron to cognition via computational neuroscience, pp. 0–25, 2011

    work page 2011

  63. [63]

    Theory for the development of neuron selec- tivity: orientation specificity and binocular interaction in visual cortex,

    E. L. Bienenstock, L. N. Cooper, and P. W. Munro, “Theory for the development of neuron selec- tivity: orientation specificity and binocular interaction in visual cortex,”Journal of Neuroscience, vol. 2, no. 1, pp. 32–48, 1982

    work page 1982

  64. [64]

    SpikeProp: backpropagation for networks of spiking neurons.,

    S. M. Bohte, J. N. Kok, and J. A. La Poutr´e, “SpikeProp: backpropagation for networks of spiking neurons.,” inESANN, vol. 48, pp. 419–424, Bruges, 2000

    work page 2000

  65. [65]

    Generalization of backpropagation with application to a recurrent gas market model,

    P. J. Werbos, “Generalization of backpropagation with application to a recurrent gas market model,” Neural Networks, vol. 1, no. 4, pp. 339–356, 1988

    work page 1988

  66. [66]

    Synaptic plasticity dynamics for deep continuous local learning (DECOLLE),

    J. Kaiser, H. Mostafa, and E. Neftci, “Synaptic plasticity dynamics for deep continuous local learning (DECOLLE),”Frontiers in Neuroscience, vol. 14, p. 424, 2020

    work page 2020

  67. [67]

    Opportunities for neuromorphic computing algorithms and applications,

    C. D. Schuman, S. R. Kulkarni, M. Parsa, J. P. Mitchell, P. Date, and B. Kay, “Opportunities for neuromorphic computing algorithms and applications,” Nature Computational Science, vol. 2, no. 1, pp. 10–19, 2022

    work page 2022

  68. [68]

    A taxonomy for computer architectures,

    D. B. Skillicorn, “A taxonomy for computer architectures,”Computer, vol. 21, no. 11, pp. 46–57, 1988

    work page 1988

  69. [69]

    Advanced dedicated hardware for simulating biologically inspired neural networks,

    D. Jung, N. Mehrtash, and H. Klar, “Advanced dedicated hardware for simulating biologically inspired neural networks,” vol. 2005, pp. 1737–1740, 2005

    work page 2005

  70. [70]

    Synaptic plasticity in spiking neural networks (SP/sup 2/INN): a system approach,

    N. Mehrtash, D. Jung, H. H. Hellmich, T. Schoenauer, V . T. Lu, and H. Klar, “Synaptic plasticity in spiking neural networks (SP/sup 2/INN): a system approach,” IEEE transactions on neural 30/39 networks, vol. 14, no. 5, pp. 980–992, 2003

    work page 2003

  71. [71]

    A novel approach for the implementation of large scale spiking neural networks on FPGA hardware,

    B. Glackin, T. M. McGinnity, L. P. Maguire, Q. Wu, and A. Belatreche, “A novel approach for the implementation of large scale spiking neural networks on FPGA hardware,” inComputational Intelligence and Bioinspired Systems, Proceedings (J. Cabestany, A. Prieto, and F. Sandoval, eds.), vol. 3512 of Lecture Notes in Computer Science, pp. 552–563, 2005

    work page 2005

  72. [72]

    Glackin, L

    B. Glackin, L. P. Maguire, T. M. McGinnity, A. Belatreche, and Q. Wu, Implementation of a biologically realistic spiking neuron model on FPGA hardware . Proceedings of the 8th Joint Conference on Information Sciences, V ols 1-3, 2005

    work page 2005

  73. [73]

    Hardware implementa- tion of Spiking Neural Network classifiers based on backpropagation-based learning algorithms,

    M. A. Nuno-Maganda, M. Arias-Estrada, C. Torres-Huitzil, and B. Girau, “Hardware implementa- tion of Spiking Neural Network classifiers based on backpropagation-based learning algorithms,” pp. 2294–2301, 2009

    work page 2009

  74. [74]

    K. L. Rice, M. A. Bhuiyan, T. M. Taha, C. N. Vutsinas, M. C. Smith, and Ieee, FPGA Imple- mentation of Izhikevich Spiking Neural Networks for Character Recognition. 2009 International Conference on Reconfigurable Computing and Fpgas, 2009

    work page 2009

  75. [75]

    Fast classification using sparsely active spiking networks,

    H. Mostafa, B. U. Pedroni, S. Sheik, and G. Cauwenberghs, “Fast classification using sparsely active spiking networks,” Institute of Electrical and Electronics Engineers Inc., 2017

    work page 2017

  76. [76]

    Energy proportional streaming spiking neural network in a reconfigurable system,

    F. Galindo Sanchez and J. Nunez-Yanez, “Energy proportional streaming spiking neural network in a reconfigurable system,”Microprocessors and Microsystems, vol. 53, pp. 57–67, 2017

    work page 2017

  77. [77]

    Kousanakis, A

    E. Kousanakis, A. Dollas, E. Sotiriades, I. Papaefstathiou, D. N. Pnevmatikatos, A. Papoutsi, P. C. Petrantonakis, P. Poirazi, S. Chavlis, G. Kastellakis, and Ieee, An Architecture for the Acceleration of a Hybrid Leaky Integrate and Fire SNN on the Convey HC-2ex FPGA-Based Processor. 2017 Ieee 25th Annual International Symposium on Field-Programmable Cus...

    work page 2017

  78. [78]

    Spiking versus traditional neural networks for character recog- nition on FPGA platform,

    A. J. Humaidi and T. M. Kadhim, “Spiking versus traditional neural networks for character recog- nition on FPGA platform,” Journal of Telecommunication, Electronic and Computer Engineering, vol. 10, no. 3, pp. 109–115, 2018

    work page 2018

  79. [79]

    Implementation of a 12-Million Hodgkin-Huxley Neuron Network on a Single Chip,

    B. Ahn, “Implementation of a 12-Million Hodgkin-Huxley Neuron Network on a Single Chip,” Association for Computing Machinery, 2020

    work page 2020

  80. [80]

    Hodgkin-Huxley-Based Neural Simulation with Networks Connecting to Near-Neighbor Neurons,

    M. Ogaki and Y . Sato, “Hodgkin-Huxley-Based Neural Simulation with Networks Connecting to Near-Neighbor Neurons,” in2021 IEEE 32nd International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp. 109–116, July 2021

    work page 2021

Showing first 80 references.