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The Open-Source BlackParrot-BedRock Cache Coherence System

T0 review · 3 major / 4 minor · reviewed 2026-08-16 · deepseek-v4-flash

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Pith's one-line read Programmable cache coherence can match fixed-function engines

desk verdict A solid engineering dissertation that delivers an open-source programmable coherence system with real measurements, though the headline performance claim is not tested at the protocol's serialization bottleneck. read the letter →

arxiv 2505.00962 v1 pith:TPJWPJD5 submitted 2025-05-02 cs.AR

Mark Unruh Wyse This is my paper · ORCID
classification cs.AR
keywords cachecoherenceprogrammableengineMOESIFprotocoldirectory-basedRISC-VmulticoreBlackParrot-BedRockmicrocode-programmabledirectoryopen-sourcehardware
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This dissertation argues that cache coherence controllers can be made programmable—able to change protocol behavior after fabrication or adapt to applications—without sacrificing the performance or area efficiency of fixed-function hardware. To show this, it presents the BedRock coherence protocol, which keeps all cache blocks in stable MOESIF states by letting the coherence directory serialize every transaction per way group. It then describes three full directory implementations inside the open-source BlackParrot multicore: a fixed-function finite-state machine, a microcode-programmable engine, and a hybrid of the two. The programmable and hybrid engines match the fixed-function design's request-processing occupancy and Splash-3 benchmark results, with a small reported area overhead relative to the whole multicore. The thesis is that programmability in the coherence system is feasible today and can be studied in an open-source setting.

What carries the argument

The central objects are the way group and the pending bit. A way group collects one tag set from every cache in the system for a single cache set, and the pending bit allows only one active coherence transaction per way group. Because the CCE is the only component that changes coherence state and it always waits for the coherence acknowledgment before clearing the pending bit, the protocol never exposes transient states, which dramatically simplifies verification and the cache controller logic. The microcode-programmable CCE uses a small base ISA plus coherence-specific instructions for flag, directory, and queue operations to process BedRock's messages, while the hybrid CCE runs a fixed-function request pipe and a programmable pipe side by side. This machinery is what lets the dissertation compare protocol-processing occupancy directly across the three designs.

What would settle it

Run a many-core workload whose address stream is deliberately hashed so that a small number of way groups receive all the coherence traffic, then measure request throughput against the same workload with addresses hashed evenly. If the programmable or hybrid CCE's throughput collapses relative to the fixed-function design under way-group contention, the programmability-without-overhead claim fails for that regime.

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Extended reading notes

Core claim

The central claim is that adding programmability to the cache coherence directory does not inherently require significant performance or area cost. The evidence is the BP-BedRock system, in which a microcode-programmable CCE and a hybrid CCE both achieve request-processing occupancy and benchmark performance comparable to the fixed-function FSM CCE, while occupying minimal additional area relative to the full multicore. BedRock itself is the enabling protocol design: it is a directory-based invalidate protocol using MOESIF states with no transient coherence states, because the directory is the sole arbiter of state changes and one pending bit per way group serializes all transactions touching that way group. The directory's full-duplicate tag sets give it exact knowledge of every cached block, so cache-to-cache transfers and upgrades can be scheduled without races. Together the protocol and the three engines demonstrate that programmable coherence is implementable and competitive, not just theoretically attractive.

Load-bearing premise

The load-bearing premise is that serializing all coherence transactions touching the same way group with a single pending bit does not become a performance bottleneck when many cores miss to addresses that map to the same group; if that serialization ever becomes the bottleneck, the programmable engines' competitive standing is lost.

Editorial extensions

If this is right

  • A protocol without transient states verifies dramatically faster: CMurphi checks the BedRock MESI variant up to 66x faster than a traditional MESI protocol with six caches, completing in hours where the traditional model would take months.
  • Because the duplicate-tag directory has a constant 6.25% storage overhead relative to L1 capacity regardless of core count, the directory can be tiled across cores with a fixed per-tile size.
  • A microcode-programmable coherence engine can match fixed-function request occupancy on common MOESIF protocol paths, so a chip could ship one programmable directory and later change the protocol without new hardware.
  • The hybrid CCE offers a path to fixed-function performance on common operations and programmable flexibility for uncommon or system-specific operations in the same directory.
  • All three designs are open source, giving other researchers a working multicore platform on which to prototype and evaluate coherence features.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • If the way-group serialization premise holds under adversarial access patterns, the same pending-bit mechanism could be reused for lightweight ordered or speculative transactions in the coherence system, an extension the dissertation does not explore.
  • Because the duplicate-tag directory overhead is constant while complete-directory overhead grows with core count, programmable duplicate-tag directories may become comparatively cheaper in many-core designs than traditional directory organizations.
  • A direct test of the thesis would be to program the ucode CCE with a non-MOESIF protocol, such as a coherence scheme tailored to accelerators, and measure whether the occupancy advantage persists; this is an extension beyond the paper's claims.
  • The performance-competitiveness result is demonstrated for Splash-3 and microbenchmark workloads, not for worst-case hashing, so the claim should be read as holding for typical rather than adversarial way-group contention.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 4 minor

Summary. The dissertation presents the BedRock directory-based MOESIF cache coherence protocol and three open-source implementations within the BlackParrot RISC-V multicore: a fixed-function FSM coherence directory engine, a microcode-programmable engine, and a hybrid of the two. The central claim, stated in Section 1.2 and revisited in Chapters 4 and 5, is that programmability can be added to the coherence system without significant performance or area overhead. Evidence includes exhaustive protocol tables and state-transition diagrams, occupancy tables for each engine, FPGA resource measurements, and Splash-3 and microbenchmark execution comparisons. The work also provides a protocol-complexity comparison against a canonical directory protocol, including CMurphi verification results for the MESI variant and a mathematical latency model for both protocols.

Significance. If the central claim holds, this is a solid, reproducible systems contribution: it ships an open-source, well-documented programmable coherence engine inside a real multicore, with machine-readable protocol artifacts and clear occupancy/area accounting. The three-engine comparison is a useful data point for a long-standing architectural question. The work is explicit about its parameter-free methodology, and the open-source release (Section 4) makes the measurements independently checkable. The main significance is therefore as an engineering demonstration and an open research platform, not as a new protocol concept; the protocol itself is a simplified directory protocol whose novelty lies in the elimination of exposed transient states and directory-controlled replacements.

major comments (3)
  1. [§4.3.1, §4.6, Tables 4.10/4.18/4.19] The performance-competitiveness claim is not tested where the protocol's serialization point is exposed. Section 4.3.1 states that only one coherence transaction per way group may be active, enforced by a pending bit, and that all requests to that way group stall at the directory. The occupancy comparison in Tables 4.10, 4.18, and 4.19 shows the ucode and hybrid engines have higher per-request occupancy than the FSM engine, but the evaluation in Section 4.6 and Chapter 5 reports only aggregate Splash-3 and microbenchmark execution times, without way-group conflict counts, pending-bit stall cycles, or access-pattern variance. Under realistic or adversarial contention on a single way group, the higher occupancy directly becomes lower throughput. This is a load-bearing gap because the thesis's central claim is parity with the fixed-function design; the manuscript should either measure contention directly or qualify the claim to no-contention and low-contention regimes.
  2. [§3.4, Table 3.10; §4.4–4.5] The verification evidence covers only the MESI variant, while the implemented engines run the MOESIF protocol. Table 3.10 reports CMurphi verification for BedRock MESI, and the text in Section 3.4 says only the MESI protocol has been verified. The BP-BedRock implementations described in Chapter 4 and 5 execute the MOESIF protocol with the O and F states (Tables 3.7, 4.18, and related state tables). Since O/F state interactions are precisely where directory-controlled transfers and writebacks are most complex, the correctness claim for the shipped design is not established by the reported verification. The authors should either verify the MOESIF variant or provide a rigorous argument for why MESI verification transfers to MOESIF, and should state this limitation explicitly where correctness is claimed.
  3. [§5.3, Figure 5.11] The hybrid CCE performance comparison in Chapter 5 is presented as a single aggregate result without reporting variance across runs or the configuration parameters (e.g., number of cores, cache sizes, network widths) used. Since the hybrid design's programmable pipe is the key new contribution, the evaluation should show the occupancy and execution-time relationship for the specific requests that use the programmable pipe, not only the blended result. This would make the claimed 'performance parity' of the hybrid design falsifiable and would address the way-group serialization concern raised above.
minor comments (4)
  1. [§1.2] The sentence 'programmability can be be introduced to the cache coherence system' contains a duplicated 'be'; please fix.
  2. [§3.5.5, Tables 3.14–3.15] The mathematical models use abbreviations such as 'M em', 'F ill', and 'Ack' without a legend; add a short note defining each symbol and explaining why the 'Ack' term is counted as latency for BedRock but the requester can overlap it with execution.
  3. [§4.3.3, Figure 4.15] The caption of Figure 4.15 contains 'T able' instead of 'Table'; also, the y-axis label 'Directory Storage Overhead' should specify the normalization basis (L1 cache capacity) directly in the axis title.
  4. [§4.2.2, Table 4.2] The description of the 'Set State & Transfer & Writeback (dirty)' occupancy of '2 + (2*N)' cycles is clear, but the table would benefit from an explicit note that N is the cache block width divided by the fill width, as defined in Section 4.2.2.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the central performance and area claims rest on direct measurements of open-source implementations, on internal occupancy tables, and on model-checking runs, not on fitted parameters or load-bearing self-citations.

full rationale

Every load-bearing result in this dissertation is evaluated empirically or by deterministic analysis within the document itself. The central comparison among the fixed-function FSM CCE, the microcode-programmable ucode CCE, and the hybrid CCE is supported by request-occupancy tables (Tables 4.10, 4.18, 4.19, 5.2, 5.5), Splash-3 normalized execution time (Figure 4.22), FPGA resource utilization (Appendix E), and microbenchmark measurements (Section 5.3). These are direct measurements of the described designs; no parameter is fitted to force performance parity, and no 'prediction' is obtained by renaming a fitted constant. The BedRock protocol description in Chapter 3 is a specification rather than a derived result: the comparisons to a canonical directory protocol are based on explicit state-transition tables, message-equivalency analysis (Table 3.13), and CMurphi model-checking runs (Section 3.4), all self-contained or machine-checked. Self-citations to BlackParrot and the BedRock protocol specification identify the prior platform and protocol, but the new contribution--three coherence-engine implementations and their measured trade-offs--does not reduce to those citations. The weakest point noted by a skeptical reader is the way-group serialization assumption (Section 4.3.1), which may limit the generality of the performance-competitiveness claim under adversarial contention; that is an evaluation-coverage concern, not a circular dependency. No circular step meeting the quoted-evidence standard was found.

Assumptions & free parameters 0 free parameters · 4 assumptions · 0 invented entities

No numeric parameters are fitted to data in this dissertation. Design choices such as L1 cache capacity, associativity, and block size are configuration parameters documented in Chapter 2, not fitted to make results match. The axioms listed are the load-bearing assumptions that the protocol and implementation rest on; they are clearly stated in the text.

assumptions (4)
  • domain assumption Coherence networks deliver messages error-free and may be unordered.
    Section 3.1.1 states this as a requirement; the protocol's race-free design depends on this assumption.
  • domain assumption Cache controllers process coherence commands atomically as indivisible operations.
    Section 3.2.5 lists this as a protocol assumption; it is load-bearing for the elimination of transient states.
  • ad hoc to paper Only one coherence transaction per way group is active at a time, enforced by pending bits.
    Section 4.3.1 introduces way groups and pending bits to serialize transactions; this implementation choice is specific to BP-BedRock and directly enables the claim of race-free operation.
  • standard math The CMurphi verification model with a single cache block and a single directory is sufficient for coherence correctness.
    Section 3.4 justifies this because coherence is per-address and directories are independent; this mathematical reduction is standard for this kind of verification.

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Cite this review

Pith. "Pith review of The Open-Source BlackParrot-BedRock Cache Coherence System." pith.science (2026). https://pith.science/paper/TPJWPJD5

@misc{pith2026250500962,
  author       = {Pith},
  title        = {Pith review of: The Open-Source BlackParrot-BedRock Cache Coherence System},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/TPJWPJD5}},
  note         = {Machine review of arXiv:2505.00962}
}
read the original abstract

This dissertation revisits the topic of programmable cache coherence engines in the context of modern shared-memory multicore processors. First, the open-source BedRock cache coherence protocol is described. BedRock employs the canonical MOESIF coherence states and reduces implementation burden by eliminating transient coherence states from the protocol. The protocol's design complexity, concurrency, and verification effort are analyzed and compared to a canonical directory-based invalidate coherence protocol. Second, the architecture and microarchitecture of three separate cache coherence directories implementing the BedRock protocol within the BlackParrot 64-bit RISC-V multicore processor, collectively called BlackParrot-BedRock (BP-BedRock), are described. A fixed-function coherence directory engine implementation provides a baseline design for performance and area comparisons. A microcode-programmable coherence directory implementation demonstrates the feasibility of implementing a programmable coherence engine capable of maintaining sufficient protocol processing performance. A hybrid fixed-function and programmable coherence directory blends the protocol processing performance of the fixed-function design with the programmable flexibility of the microcode-programmable design. Collectively, the BedRock coherence protocol and its three BP-BedRock implementations demonstrate the feasibility and challenges of including programmable logic within the coherence system of modern shared-memory multicore processors, paving the way for future research into the application- and system-level benefits of programmable coherence engines.

Figures

Figures reproduced from arXiv: 2505.00962 by the authors.

Figure 2
Figure 2. [PITH_FULL_IMAGE:figures/full_fig_p019_2.png] view at source ↗
Figure 2.1
Figure 2.1. Canonical Shared-Memory Multicore Processor Architecture [PITH_FULL_IMAGE:figures/full_fig_p020_2_1.png] view at source ↗
Figure 2.2
Figure 2.2. The Cache Coherence Problem in the system. A detailed discussion of memory consistency is beyond the scope of this dissertation. Cache coherence, on the other hand, defines the ordering and outcomes of read and write operations made by more than one processing element to a single memory location in a system employing private data caches that hold local copies of memory data. In many systems, cache coherence defines … view at source ↗
Figures from the paper (93 more)
Figure 2
Figure 2. Figure 2: a [PITH_FULL_IMAGE:figures/full_fig_p021_2.png]
Figure 2.3
Figure 2.3. Figure 2.3: Cache Coherence Single Writer Multiple Reader (SWMR) Invariant [PITH_FULL_IMAGE:figures/full_fig_p022_2_3.png]
Figure 2
Figure 2. Figure 2 [PITH_FULL_IMAGE:figures/full_fig_p022_2.png]
Figure 2.4
Figure 2.4. Figure 2.4: Cache Coherence Data Value Invariant location is guaranteed to be identical. Data Value Invariant The Data Value Invariant, depicted in [PITH_FULL_IMAGE:figures/full_fig_p023_2_4.png]
Figure 2.5
Figure 2.5. Figure 2.5: BlackParrot Tiled Multicore Processor core complex is configurable and supports most common organizations. The remaining tile types surround the core complex in 1-dimensional complexes. Along the North side of the core complex are the I/O tiles, which connect off-chi…
Figure 2
Figure 2. Figure 2 [PITH_FULL_IMAGE:figures/full_fig_p024_2.png]
Figure 2.6
Figure 2.6. Figure 2.6: BlackParrot Multicore Tiles I/O and streaming accelerator tiles. These tiles only support uncached load and store operations, and therefore do not utilize the Fill or Response BedRock networks. DRAM Network The DRAM network supports both cacheable and uncacheable mem…
Figure 2
Figure 2. Figure 2: a [PITH_FULL_IMAGE:figures/full_fig_p025_2.png]
Figure 2
Figure 2. Figure 2: b [PITH_FULL_IMAGE:figures/full_fig_p026_2.png]
Figure 2.7
Figure 2.7. Figure 2.7: BlackParrot Physical Address Space maintaining coherence between the off-chip and DRAM domains. In practice, off-chip I/O access to cacheable DRAM addresses is used to load software or data for execution into BlackParrot’s DRAM prior to the processor cores beginning …
Figure 2
Figure 2. Figure 2: c [PITH_FULL_IMAGE:figures/full_fig_p027_2.png]
Figure 2.8
Figure 2.8. Figure 2.8: BlackParrot Cache Engine Interface is not managed by the BedRock coherence protocol. The BlackParrot Platform Guide found in the BlackParrot documentation provides a more detailed breakdown of the local memory region. Cacheable Global Memory Cacheable global memory i…
Figure 2
Figure 2. Figure 2 [PITH_FULL_IMAGE:figures/full_fig_p028_2.png]
Figure 2
Figure 2. Figure 2: a [PITH_FULL_IMAGE:figures/full_fig_p029_2.png]
Figure 3.1
Figure 3.1. Figure 3.1: Canonical BedRock Coherence System Organization [PITH_FULL_IMAGE:figures/full_fig_p031_3_1.png]
Figure 3
Figure 3. Figure 3 [PITH_FULL_IMAGE:figures/full_fig_p031_3.png]
Figure 3.2
Figure 3.2. Figure 3.2: BedRock Coherence Networks Request Network The Request network carries messages from a cache controller to a coherence directory. Coherence requests are initiated when a cache miss occurs due to the cache having insufficient permissions to complete the requested oper…
Figure 3.3
Figure 3.3. Figure 3.3: Canonical BedRock Coherence Directory Request Processing Flow [PITH_FULL_IMAGE:figures/full_fig_p034_3_3.png]
Figure 3
Figure 3. Figure 3 [PITH_FULL_IMAGE:figures/full_fig_p034_3.png]
Figure 3.4
Figure 3.4. Figure 3.4: Canonical Address Space Layout and Cacheability Properties [PITH_FULL_IMAGE:figures/full_fig_p036_3_4.png]
Figure 3
Figure 3. Figure 3 [PITH_FULL_IMAGE:figures/full_fig_p036_3.png]
Figure 3.5
Figure 3.5. Figure 3.5: BedRock I→S Transitions (1) ReqRd (3) CohAck (2) Data Req IE Dir IE [PITH_FULL_IMAGE:figures/full_fig_p052_3_5.png]
Figure 3.6
Figure 3.6. Figure 3.6: BedRock I→E Transitions 38 [PITH_FULL_IMAGE:figures/full_fig_p052_3_6.png]
Figure 3.7
Figure 3.7. Figure 3.7: BedRock I/S→M Transitions (1) ReqWr (3) CohAck (2) STW Req FM OM Dir FM OM Req FM OM Dir FM OM Sharer SI (3) InvAck (2) Inv (1) ReqWr (3) CohAck Sharer SI (2) Inv (2) STW (3) InvAck [PITH_FULL_IMAGE:figures/full_fig_p053_3_7.png]
Figure 3.8
Figure 3.8. Figure 3.8: BedRock F/O→M Transitions 39 [PITH_FULL_IMAGE:figures/full_fig_p053_3_8.png]
Figure 3.9
Figure 3.9. Figure 3.9: Canonical I→S Transitions (1) GetS (2) Data Req IE Dir IE [PITH_FULL_IMAGE:figures/full_fig_p054_3_9.png]
Figure 3.10
Figure 3.10. Figure 3.10: Canonical I→E Transitions 40 [PITH_FULL_IMAGE:figures/full_fig_p054_3_10.png]
Figure 3.11
Figure 3.11. Figure 3.11: Canonical I/S→M Transitions (1) GetM (2) AckCount[ack=0] Req FM OM Dir FM OM Req FM OM Dir FM OM Sharer SI (3) Inv-Ack (2) Inv (1) GetM Sharer SI (2) Inv (2) AckCount[ack>0] (3) Inv-Ack [PITH_FULL_IMAGE:figures/full_fig_p055_3_11.png]
Figure 3.12
Figure 3.12. Figure 3.12: Canonical F/O→M Transitions 41 [PITH_FULL_IMAGE:figures/full_fig_p055_3_12.png]
Figure 3
Figure 3. Figure 3 [PITH_FULL_IMAGE:figures/full_fig_p056_3.png]
Figure 3
Figure 3. Figure 3 [PITH_FULL_IMAGE:figures/full_fig_p057_3.png]
Figure 4
Figure 4. Figure 4 [PITH_FULL_IMAGE:figures/full_fig_p061_4.png]
Figure 4.1
Figure 4.1. Figure 4.1: BP-Bedrock Stream Protocol ‘ define declare_bp_bedrock_header_s ( addr_width_mp , payload_mp , name_mp ) \ typedef struct packed \ { \ payload_mp payload ; \ bp_bedrock_msg_size_e size ; \ logic [ addr_width_mp -1:0] addr ; \ bp_bedrock_wr_subop_e subop ; \ bp_bedroc…
Figure 4.2
Figure 4.2. Figure 4.2: BP-BedRock LCE Block Diagram header and data signals that can be examined by the protocol processing logic to easily take action at important points in messaging processing. The new signal is asserted on the first beat of a message, the last signal is asserted on the…
Figure 4
Figure 4. Figure 4 [PITH_FULL_IMAGE:figures/full_fig_p063_4.png]
Figure 4.3
Figure 4.3. Figure 4.3: BP-BedRock LCE Request Block Diagram Crossbar before being processed by the Command FSM. The BP-BedRock LCE supports cacheable, uncacheable, and atomic read-modify-write operations to lower levels of the memory hierarchy. As discussed in Section 2.3, the BP-BedRock L…
Figure 4
Figure 4. Figure 4 [PITH_FULL_IMAGE:figures/full_fig_p064_4.png]
Figure 4.4
Figure 4.4. Figure 4.4: BP-BedRock LCE Request FSM Cache Request Occupancy (cycles) Initiation Interval (cycles) Description Cacheable Load, Cacheable Store 2 + N – Block-based cache miss, send cacheable miss request Uncacheable Load 2 + N – 1, 2, 4, or 8-byte load, send uncached load reque…
Figure 4.5
Figure 4.5. Figure 4.5: BP-BedRock LCE Command Block Diagram Reset Clear Ready Send Ack Transfer Stat Clear Writeback [PITH_FULL_IMAGE:figures/full_fig_p066_4_5.png]
Figure 4.6
Figure 4.6. Figure 4.6: BP-BedRock LCE Command State Machine request in the Ready state and then both receiving the valid metadata and sending the outbound coherence requst in the Send Request state in the same cycle. Thus, the extra cycle of occupancy is a consequence of the BP-BedRock L1 …
Figure 4
Figure 4. Figure 4 [PITH_FULL_IMAGE:figures/full_fig_p066_4.png]
Figure 4
Figure 4. Figure 4 [PITH_FULL_IMAGE:figures/full_fig_p069_4.png]
Figure 4.7
Figure 4.7. Figure 4.7: BP-BedRock Coherence Directory Architecture [PITH_FULL_IMAGE:figures/full_fig_p070_4_7.png]
Figure 4.8
Figure 4.8. Figure 4.8: BP-BedRock Tag Set modification, and each segment’s outputs are either combined or multiplexed to the output ports of the coherence directory. If no coherent accelerators are present in the design, the accelerator cache directory segment is not instantiated. 4.3.1 Ta…
Figure 4
Figure 4. Figure 4 [PITH_FULL_IMAGE:figures/full_fig_p070_4.png]
Figure 4.9
Figure 4.9. Figure 4.9: BP-BedRock Way Group Pending Bit Cache 1 - Tag Set 1 Way Group 1 Cache 2 - Tag Set 1 Cache N - Tag Set 1 Pending Bit Cache 1 - Tag Set 2 Way Group 2 Cache 2 - Tag Set 2 Cache N - Tag Set 2 Pending Bit Cache 1 - Tag Set 3 Way Group 3 Cache 2 - Tag Set 3 Cache N - Tag …
Figure 4.10
Figure 4.10. Figure 4.10: BP-BedRock Way Groups At all times, the tag sets tracked at the coherence directory are considered to be the golden copies of the tag sets, which hold the current state of the coherence system across all cached blocks. The directory updates its tag sets during reque…
Figure 4
Figure 4. Figure 4 [PITH_FULL_IMAGE:figures/full_fig_p071_4.png]
Figure 4.11
Figure 4.11. Figure 4.11: BP-BedRock Address Breakdown block that maps to cache set X (equivalently, tag set X), is a member of way group X [PITH_FULL_IMAGE:figures/full_fig_p072_4_11.png]
Figure 4.12
Figure 4.12. Figure 4.12: illustrates how cache blocks in two caches with different organizations may be related. Cache A has S sets and Cache B has 2*S sets. A cache block that maps to set N in Cache A may map to either set N or S+N in Cache B. Conversely, a block that maps to either set N …
Figure 4
Figure 4. Figure 4 [PITH_FULL_IMAGE:figures/full_fig_p073_4.png]
Figure 4.13
Figure 4.13. Figure 4.13: BP-BedRock Coherence Directory Segment 4.3.2 Coherence Directory Segment Architecture Directory Segment Storage [PITH_FULL_IMAGE:figures/full_fig_p074_4_13.png]
Figure 4.14
Figure 4.14. Figure 4.14: BP-BedRock Sharers Vectors ID bits. The least significant bits determine the cache’s position within a row, and the remaining bits index a lookup table that provides the row within the directory memory. The lookup table is computed at compilation and provides fast-a…
Figure 4
Figure 4. Figure 4 [PITH_FULL_IMAGE:figures/full_fig_p075_4.png]
Figure 4.15
Figure 4.15. Figure 4.15: Coherence Directory Storage Overhead Comparison [PITH_FULL_IMAGE:figures/full_fig_p076_4_15.png]
Figure 4
Figure 4. Figure 4 [PITH_FULL_IMAGE:figures/full_fig_p077_4.png]
Figure 4
Figure 4. Figure 4 [PITH_FULL_IMAGE:figures/full_fig_p078_4.png]
Figure 4.16
Figure 4.16. Figure 4.16: BP-Bedrock FSM CCE Block Diagram track speculative memory reads issued during request processing, Pending Bits to enforce coherence transaction ordering for each way group, and a Flow Counter to provide network flow control on the memory network. The LCE Request sta…
Figure 4
Figure 4. Figure 4 [PITH_FULL_IMAGE:figures/full_fig_p083_4.png]
Figure 4.17
Figure 4.17. Figure 4.17: BP-Bedrock FSM CCE Memory Response Abstract State Machine [PITH_FULL_IMAGE:figures/full_fig_p084_4_17.png]
Figure 4.18
Figure 4.18. Figure 4.18: BP-Bedrock FSM LCE Request State Machine [PITH_FULL_IMAGE:figures/full_fig_p085_4_18.png]
Figure 4
Figure 4. Figure 4 [PITH_FULL_IMAGE:figures/full_fig_p087_4.png]
Figure 4.19
Figure 4.19. Figure 4.19: BP-BedRock Microcode-Programmable CCE Block Diagram [PITH_FULL_IMAGE:figures/full_fig_p089_4_19.png]
Figure 4.20
Figure 4.20. Figure 4.20: BP-BedRock MOESIF Microcode Processing Flow - Initial and Fast Path [PITH_FULL_IMAGE:figures/full_fig_p097_4_20.png]
Figure 4.21
Figure 4.21. Figure 4.21: BP-BedRock MOESIF Microcode Processing Flow - Slow Path [PITH_FULL_IMAGE:figures/full_fig_p097_4_21.png]
Figure 4
Figure 4. Figure 4 [PITH_FULL_IMAGE:figures/full_fig_p097_4.png]
Figure 4
Figure 4. Figure 4 [PITH_FULL_IMAGE:figures/full_fig_p098_4.png]
Figure 4.22
Figure 4.22. Figure 4.22: BP-BedRock Splash-3 Normalized Execution Time - 8 core [PITH_FULL_IMAGE:figures/full_fig_p102_4_22.png]
Figure 4
Figure 4. Figure 4 [PITH_FULL_IMAGE:figures/full_fig_p102_4.png]
Figure 5
Figure 5. Figure 5 [PITH_FULL_IMAGE:figures/full_fig_p104_5.png]
Figure 5.1
Figure 5.1. Figure 5.1: Hybrid CCE Block Diagram processed by either the Uncacheable Request Pipe or the Coherent Request Pipe after first being classified by the Request Arbiter block. The rest of this section describes the functionality of each processing pipe and the other major modules …
Figure 5
Figure 5. Figure 5 [PITH_FULL_IMAGE:figures/full_fig_p105_5.png]
Figure 5.2
Figure 5.2. Figure 5.2: Hybrid CCE Coherence State and Pipe Interaction [PITH_FULL_IMAGE:figures/full_fig_p106_5_2.png]
Figure 5.3
Figure 5.3. Figure 5.3: Hybrid CCE Control State Machine The Memory Command crossbar arbitrates access to the outbound memory command interface from the uncacheable request, coherent request, and LCE response pipelines. During normal op￾eration, the majority of memory commands are issued by…
Figure 5
Figure 5. Figure 5 [PITH_FULL_IMAGE:figures/full_fig_p106_5.png]
Figure 5.4
Figure 5.4. Figure 5.4: Hybrid CCE Coherent Request Pipe Block Diagram [PITH_FULL_IMAGE:figures/full_fig_p107_5_4.png]
Figure 5
Figure 5. Figure 5 [PITH_FULL_IMAGE:figures/full_fig_p107_5.png]
Figure 5
Figure 5. Figure 5 [PITH_FULL_IMAGE:figures/full_fig_p108_5.png]
Figure 5.5
Figure 5.5. Figure 5.5: Hybrid CCE Coherent Request Pipe State Machine [PITH_FULL_IMAGE:figures/full_fig_p109_5_5.png]
Figure 5
Figure 5. Figure 5 [PITH_FULL_IMAGE:figures/full_fig_p109_5.png]
Figure 5
Figure 5. Figure 5 [PITH_FULL_IMAGE:figures/full_fig_p111_5.png]
Figure 5.6
Figure 5.6. Figure 5.6: BP-Bedrock Hybrid CCE Memory Response Pipe Block Diagram [PITH_FULL_IMAGE:figures/full_fig_p112_5_6.png]
Figure 5
Figure 5. Figure 5 [PITH_FULL_IMAGE:figures/full_fig_p112_5.png]
Figure 5.8
Figure 5.8. Figure 5.8: Hybrid CCE LCE Response Pipe Block Diagram [PITH_FULL_IMAGE:figures/full_fig_p113_5_8.png]
Figure 5.9
Figure 5.9. Figure 5.9: Hybrid CCE LCE Response Pipe State Machine [PITH_FULL_IMAGE:figures/full_fig_p114_5_9.png]
Figure 5
Figure 5. Figure 5 [PITH_FULL_IMAGE:figures/full_fig_p114_5.png]
Figure 5.10
Figure 5.10. Figure 5.10: Hybrid CCE Programmable Pipe Block Diagram [PITH_FULL_IMAGE:figures/full_fig_p115_5_10.png]
Figure 5
Figure 5. Figure 5 [PITH_FULL_IMAGE:figures/full_fig_p119_5.png]
Figure 5.11
Figure 5.11. Figure 5.11: Hybrid CCE Performance Comparison [PITH_FULL_IMAGE:figures/full_fig_p120_5_11.png]
Figure 5.12
Figure 5.12. Figure 5.12: FPGA Resource Utilization Overheads - Full Design [PITH_FULL_IMAGE:figures/full_fig_p121_5_12.png]
Figure 5
Figure 5. Figure 5 [PITH_FULL_IMAGE:figures/full_fig_p121_5.png]
Figure 5.13
Figure 5.13. Figure 5.13: FPGA Resource Utilization Overheads - BlackParrot Multicore [PITH_FULL_IMAGE:figures/full_fig_p122_5_13.png]
Figure 5
Figure 5. Figure 5 [PITH_FULL_IMAGE:figures/full_fig_p122_5.png]

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