Pith. sign in

REVIEW 4 major objections 5 minor 41 references

Bridging Quantized Artificial Neural Networks and Neuromorphic Hardware

T0 review · 4 major / 5 minor · reviewed 2026-08-15 · deepseek-v4-flash

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗ Review JSON

Pith's one-line read The paper claims SDANN runs quantized ReLU ANNs on neuromorphic hardware with exactly the quantized accuracy and no retraining.

desk verdict A genuinely useful mapping from quantized ANNs to spike-based hardware, but the 'exact' claim only holds without scaled integration and the hardware validation omits accuracy numbers. read the letter →

arxiv 2505.12221 v2 pith:ZYLIWJ6H submitted 2025-05-18 cs.NE

Zhenhui Chen , Haoran Xu , Yangfan Hu , Xiaofei Jin , Xinyu Li , Ziyang Kang , Gang Pan , De Ma This is my paper · ORCID
classification cs.NE
keywords quantizedneuralnetworksneuromorphichardwarespikingneuronANN-to-SNNconversionbinaryspikeencodingscaledintegrationenergy-efficientinferenceReLU
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Spiking neural networks have long been the bridge from deep learning to neuromorphic hardware, but they pay a conversion or training cost. This paper proposes a different bridge: take a standard uniform 8-bit quantized ANN with ReLU activations and execute its integer arithmetic directly with spike trains, one binary bit per time step. The claim is that the resulting spiking model, called SDANN, reproduces the quantized ANN's accuracy exactly, with no retraining and no tuning of trained parameters. If true, any existing quantized ReLU network could be deployed on spike-based hardware with a guaranteed performance floor.

What carries the argument

The Spike-Timing Encoder-Decoder Model (STEM): a spiking neuron that decodes a signed K-bit integer from an incoming binary spike train, computes the layer's weighted sum while scaling each bit's contribution by M0 = ($2^{{n-1}}$-1)/I_max, and re-encodes the ReLU output as a spike train using thresholds $2^{{2K-t-1}}$. Bias calibration, which sets the bias scale S_b equal to the activation scale S_a, is the companion device that keeps quantized biases within 8-bit range. Together they turn a multiply-accumulate ANN layer into purely additive, event-driven operations whose result is bit-for-bit the integer arithmetic of the quantized network.

What would settle it

Feed the SDANN model on Darwin3 (or its software simulation) an input intentionally constructed so that a neuron's raw synaptic current exceeds the recorded I_max—for example, an image whose first-layer activations are all at their maximum quantized magnitude—and check whether the 16-bit accumulator wraps; if the output then differs from the quantized ANN's output, the exactness claim fails. A purely computational version: compute, per layer, the theoretical maximum of |sum_j W_ij X_j| over the 8-bit ranges and compare it with I_max.

Watch

Extended reading notes

Core claim

The central discovery is a four-phase spiking neuron model, STEM, that makes the quantized ANN's computation bit-exact. Input activations arrive as binary spike trains; the neuron accumulates, for each bit position, the weighted sum contributed by that bit; scaled integration multiplies each time-step's contribution by a factor M0 obtained from the maximum observed synaptic current, preventing overflow in a 16-bit accumulator; bias calibration sets the bias scale equal to the activation scale so the bias fits narrow hardware integers. After K accumulation steps the neuron's membrane value is the scaled integer pre-activation, ReLU is applied by construction, and a generation phase emits an output spike train that encodes the quantized activation bit by bit. The paper verifies that SDANN accuracy equals quantized ANN accuracy to the last reported digit on CIFAR-10, ImageNet-1k, and VOC2007, and reports a deployment on Darwin3 hardware.

Load-bearing premise

The exactness of the mapping depends on I_max, the maximum synaptic current used to set the scaling factor M0, being a true upper bound over all possible inputs, but the paper derives it from statistics collected during quantization on sample images rather than from an analytical worst-case bound.

Editorial extensions

If this is right

  • Any uniform 8-bit quantized ReLU ANN can be executed on spike-based neuromorphic hardware with no conversion loss and no retraining, giving a guaranteed accuracy floor.
  • Inference becomes event-driven: costly multiply-accumulates become pure accumulations, and the estimated energy per inference on Darwin3 is about one to two orders of magnitude below a GPU baseline.
  • Because the mapping is exact, large pretrained quantized models (up to 12M parameters in the paper) can be deployed on neuromorphic hardware at scales previously reached only by dedicated SNNs.
  • Optional layer-wise spike sparsification (RoT and DRLOs) trades a small accuracy drop for a large cut in spikes and energy, giving a tunable efficiency knob.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The bit-per-timestep phase encoding suggests a general recipe: any uniformly quantized, piecewise-linear activation (not just ReLU) could be emulated exactly by threshold-based firing, extending the framework to ReLU6 or quantized hard-sigmoid networks without extra training.
  • The dependence on an empirical I_max means the 'exactly the same accuracy' guarantee is distribution-dependent; deriving a per-layer analytical upper bound on the pre-activation range from weight norms and the known activation range would make the scaling overflow-proof.
  • If the exactness claim holds, the framework effectively dissolves the ANN-SNN distinction for deployment purposes: the same quantized weights and biases serve both conventional integer hardware and spiking hardware, so a single model artifact could target both platforms.
Share X Bluesky LinkedIn Reddit HN

Signed reviews

No signed human review yet.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 5 minor

Summary. The paper proposes SDANN, a framework for mapping quantized ReLU-based ANNs onto spike-based neuromorphic hardware. It introduces STEM, a spike-timing encoding that represents quantized activations as binary spike trains, together with bias calibration, scaled integration to avoid 16-bit accumulator overflow, optional spike sparsification methods (RoT and DRLOs), and pipelined execution. Software experiments report accuracy identical to the quantized ANN on CIFAR-10, ImageNet-1k, and VOC2007, and energy estimates are given for several architectures. The paper also reports deployment of Tiny-VGG and Tiny-YOLO on the Darwin3 neuromorphic chip with energy measurements. The central claim is that SDANN achieves exactly the same accuracy as the quantized ANN without retraining or performance degradation, and that the framework provides a lower bound for neuromorphic implementation performance.

Significance. If the exactness claim were fully established, this would be a practically significant bridge between quantized ANNs and neuromorphic hardware, avoiding the conversion loss and retraining costs of ANN-to-SNN approaches and enabling large models on real hardware. The paper's genuine strengths include real hardware deployment on Darwin3, quantitative energy measurements, and a systematic ablation of spike sparsification methods. However, the exactness claim is currently supported only in the software setting without scaled integration; the hardware path relies on an approximating scaling step whose error is neither quantified nor audited by hardware accuracy measurements. The engineering contribution is solid, but the advertised theoretical claim is stronger than the evidence.

major comments (4)
  1. [IV.B.2, Table III] The paper's central claim of exact accuracy is contradicted by Table III, which reports nonzero differences between the quantized ANN and SDANN with scaled integration on every model tested (e.g., Tiny-VGG on ImageNet: 53.65 vs 53.60; ResNet-34 on VOC2007: 72.82 vs 72.66). Table II's zero-difference results are obtained without scaled integration, as Section IV.B.2 states, while the hardware deployment of Section V uses scaled integration. Consequently, the abstract's claims of 'exactly the same accuracy' and 'eliminating any performance degradation' are not supported for the configuration actually deployed on Darwin3.
  2. [III.B.b, Eqs. (16)-(19)] Eqs. (16)-(19) define M0 = (2^{n-1}-1)/I_max, which is generally not an integer. Applying M0 to each I_i,t in Eq. (18) inside a 16-bit integer accumulator requires rounding or truncation of M0 * I_i,t, so the claimed equality V_i = M1 * M0 * sum_t I_i,t + b_i cannot hold bit-exactly. The paper provides no fixed-point error analysis; establishing the exactness claim requires a rounding scheme and a bound on the accumulated rounding error, or a proof that the hardware arithmetic avoids rounding altogether.
  3. [III.B.b, Eq. (16), Fig. 7] Eq. (16) uses I_max to scale the accumulated synaptic current into the representable range, but I_max is obtained as a sample maximum from 100 ImageNet images (Fig. 7), not as a worst-case bound over the input domain. If a test input produces a synaptic current larger than this empirical maximum, the 16-bit accumulator overflows and the exact mapping breaks. The authors should either derive a formal upper bound on |sum_j W_ij X_j| from the quantization ranges and fan-in, or demonstrate overflow-free operation on the full validation set and on the deployed hardware.
  4. [V, Table X] Section V reports only energy consumption (Table X) and qualitative detection images (Fig. 13) for the Darwin3 deployment; no classification accuracy or mAP measured on hardware is provided. Without a quantitative comparison between the hardware output and the quantized ANN, the central claim that SDANN preserves accuracy on real neuromorphic hardware remains unverified.
minor comments (5)
  1. [IV.A] The first bullet says 'Classification on CIFAR10: CIFAR100 [36] has 50,000 images...' but the task is CIFAR-10 and the reference to CIFAR100 appears to be a typo.
  2. [III.B, Eqs. (12)-(13), (20)-(21)] Equations such as '2K-t-1' should be typeset with explicit exponents (2^{K-t-1}) to avoid ambiguity, and the sign convention for t=0 in Eq. (13) should be stated more precisely.
  3. [Table VIII] Table VIII lists Tiny-VGG on ImageNet as 54.05% without sparsification, whereas Table II and Table III give 53.60% and 53.65% for the same configuration; these inconsistencies should be reconciled.
  4. [Fig. 12] The caption mentions PEDSNN while the text and legend use PESNN; the acronyms should be unified.
  5. [III.B.b, Eq. (15)] The claimed ideal range of the weighted sum in Eq. (15) should be derived from the signedness and bit widths of W and x; as written, it is not obvious that the bounds are correct for 8-bit signed weights and 8-bit activations.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the SDANN-to-quantized-ANN accuracy identity is explicitly a direct mapping by construction, and the remaining concerns are robustness/accuracy issues, not circular reasoning.

full rationale

The paper's central equivalence claim is not a disguised prediction from fitted parameters; it is an explicit implementation identity. The authors state: 'Notably, the performance of the SDANN model is equivalent to that of the quantized ANN model. This alignment is due to the direct mapping of SDANN with STEM to the corresponding quantized ANN.' This sentence concedes that the equality is by construction, not an empirical discovery. The derivation chain, Eqs. (11)-(21), is self-contained algebra: a quantized integer activation is expanded in binary form, the weighted sum is unrolled over bits, and the generation phase re-encodes the result into a spike train. No trainable parameter is fitted to the accuracy target, and no external 'prediction' is generated from data. The scaled-integration constants M0 and M1 are computed from I_max as engineering constants, and Table III shows that scaled integration actually introduces small nonzero gaps (e.g., Tiny-VGG 53.60 vs 53.65; ResNet-34 VOC 72.66 vs 72.82), which is evidence that the authors are not hiding fitted identity behind the claim. The use of an empirical I_max from 100 ImageNet images is a legitimate robustness concern about overflow for out-of-distribution inputs, and the abstract's 'exactly the same accuracy' is arguably overstated relative to Table III, but these are correctness/accuracy issues, not circular reasoning. Self-citations such as the Darwin3 hardware reference are background or platform references and are not load-bearing in the derivation of the equivalence. Therefore, the paper's derivation chain does not exhibit circularity, and a score of 0 is appropriate.

Assumptions & free parameters 3 free parameters · 4 assumptions · 0 invented entities

No new physical entities, forces, conserved quantities, or dimensions are postulated. STEM is a computational module and Darwin3 is an existing chip, so the invented-entities ledger is empty.

free parameters (3)
  • Per-layer quantization scale factors S_w, S_x, S_a = Derived from observed weight and activation ranges
    Standard uniform symmetric quantization maps float ranges to 8-bit integers; these factors are data-dependent constants, not fitted to the target accuracy, but they set the precision of the whole pipeline.
  • Peak synaptic current I_max for scaled integration = Not reported; statistic over 100 images
    Determines M0 in Eq. (16) and thus the fixed-point scaling during accumulation. If I_max is an empirical maximum from a small calibration set, it is a fragile calibration constant rather than a proven upper bound.
  • Per-layer sparsification factor b (RoT/DRLOs) = Varies per layer; selected on validation data
    Hyperparameters for the optional spike-reduction stage; they trade a small accuracy loss for fewer synaptic operations and are chosen per layer via the hybrid scheme.
assumptions (4)
  • domain assumption Uniform symmetric quantization with zero-point Z=0 represents the trained ANN within the reported precision.
    Section II.A sets Z=0 for hardware compatibility; the accuracy gap between full-precision and quantized ANN in Table III is the cost of this assumption.
  • domain assumption Spikes arrive at the receiving neuron in globally synchronized time slots with no temporal dispersion.
    The STEM accumulation in Eq. (14) treats each time step as an exact binary position; NoC timing jitter or event reordering would corrupt the bit weights.
  • ad hoc to paper The maximum synaptic current I_max is an upper bound for all test inputs.
    Introduced in Section III.B.b to set M0; Fig. 7 statistics come from 100 images, so the bound may be empirical rather than analytical.
  • domain assumption Darwin3 executes non-leaky accumulation, threshold comparison, and subtraction without arithmetic error inside the 16-bit accumulator.
    The hardware deployment in Section V depends on the neuron ISA reproducing Eqs. (18)-(21) bit-exactly; no quantitative hardware accuracy is reported to confirm this.

how reviews work

0 comments
Cite this review

Pith. "Pith review of Bridging Quantized Artificial Neural Networks and Neuromorphic Hardware." pith.science (2026). https://pith.science/paper/ZYLIWJ6H

@misc{pith2026250512221,
  author       = {Pith},
  title        = {Pith review of: Bridging Quantized Artificial Neural Networks and Neuromorphic Hardware},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/ZYLIWJ6H}},
  note         = {Machine review of arXiv:2505.12221}
}
read the original abstract

Neuromorphic hardware aims to leverage distributed computing and event-driven circuit design to achieve an energy-efficient AI system. The name "neuromorphic" is derived from its spiking and local computing nature, which mimics the fundamental activity of an animal's nervous system. In neuromorphic hardware, neurons, i.e., computing cores use single-bit, event-driven data (called spikes) for inter-communication, which differs substantially from conventional hardware. To leverage the advantages of neuromorphic hardware and implement a computing model, the conventional approach is to build spiking neural networks (SNNs). SNNs replace the nonlinearity part of artificial neural networks (ANNs) in the realm of deep learning with spiking neurons, where the spiking neuron mimics the basic behavior of bio-neurons. However, there is still a performance gap between SNNs and their ANN counterparts. In this paper, we explore a new way to map computing models onto neuromorphic hardware. We propose a Spiking-Driven ANN (SDANN) framework that directly implements quantized ANN on hardware, eliminating the need for tuning the trainable parameters or any performance degradation. With the power of quantized ANN, our SDANN ensures a lower bound of implementation performance on neuromorphic hardware. To address the limitation of bit width support on hardware, we propose bias calibration and scaled integration methods. Experiments on various tasks demonstrate that our SDANN achieves exactly the same accuracy as the quantized ANN. Beyond toy examples and software implementation, we successfully deployed and validated our spiking models on real neuromorphic hardware, demonstrating the feasibility of the SDANN framework.

Figures

Figures reproduced from arXiv: 2505.12221 by the authors.

Figure 1
Figure 1. Yet another way from ANN to neuromorphic hardware. [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. a) From weighted sum to dendrites and neurons. b) From spikes to spike train. c) A simple neuromorphic hardware [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figure 3
Figure 3. The workflow of SDANN framework, from ANN quantization to neuromorphic hardware implementation. [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figures from the paper (9 more)
Figure 4
Figure 4. Figure 4: The distribution of quantized bias values across logarithmically scaled intervals are as follows. In Fig. 4a, the dashed [PITH_FULL_IMAGE:figures/full_fig_p005_4.png]
Figure 6
Figure 6. Figure 6: The working flow inside STEM model a) Accumulation: decode from spikes: To perform the quantized ANN computation, we use a two-phase spiking encoding/decoding scheme, where the cell body is used to pre￾cisely compute the quantized input integers as well as output a spi…
Figure 7
Figure 7. Figure 7: Distribution statistics of quantized synaptic current: The dashed lines indicate the representable range of 16-bit integer. [PITH_FULL_IMAGE:figures/full_fig_p006_7.png]
Figure 8
Figure 8. Figure 8: Statistics of the count of 1 in each Bit position. In Eq. (14), xj,t values are confined to the set 0, 1 as the input spike train, where MACs are reduced to mere accumula￾tion (ACs) operations. When a spike arrives, the parameter W is added to It through a single addit…
Figure 9
Figure 9. Figure 9: The SOP of each layer under different spike sparsity schemes across various datasets and tasks. [PITH_FULL_IMAGE:figures/full_fig_p008_9.png]
Figure 10
Figure 10. Figure 10: Spike sparsity schemes in 8-bit IV. EXPERIMENTS AND ANALYSES Before hardware deployment, we evaluate SDANN using software simulation based on the PyTorch framework [35]. To evaluate the effectiveness of the proposed SDANN method￾ology, we conduct experiments on three …
Figure 11
Figure 11. Figure 11: Pipelining of SDANN. For clarity, we take a simple 2-layer network as an example and define [PITH_FULL_IMAGE:figures/full_fig_p009_11.png]
Figure 12
Figure 12. Figure 12: Comparison with directly trained SNN methods using [PITH_FULL_IMAGE:figures/full_fig_p010_12.png]
Figure 13
Figure 13. Figure 13: Detection results comparison of Tiny-Yolo on the PASCAL VOC 2007 test set. From left to right: full-precision ANN, [PITH_FULL_IMAGE:figures/full_fig_p013_13.png]

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

41 extracted references · 29 canonical work pages

  1. [1]

    Deep learning,

    Y . LeCun, Y . Bengio, and G. Hinton, “Deep learning,” Nature, vol. 521, no. 7553, pp. 436–444, 2015

    2015

  2. [2]

    The growing energy footprint of artificial intelligence,

    A. de Vries, “The growing energy footprint of artificial intelligence,” Joule, vol. 7, no. 10, pp. 2191–2194, 2023

    2023

  3. [3]

    Towards spike-based machine intelligence with neuromorphic computing,

    K. Roy, A. Jaiswal, and P. Panda, “Towards spike-based machine intelligence with neuromorphic computing,” Nature, vol. 575, no. 7784, pp. 607–617, 2019

    2019

  4. [4]

    A million spiking-neuron integrated circuit with a scalable communication network and interface,

    P. A. Merolla, J. V . Arthur, R. Alvarez-Icaza, A. S. Cassidy, J. Sawada, F. Akopyan, B. L. Jackson, N. Imam, C. Guo, Y . Nakamura et al., “A million spiking-neuron integrated circuit with a scalable communication network and interface,” Science, vol. 345, no. 6197, pp. 668–673, 2014

    work page 2014

  5. [5]

    Loihi: A neuromorphic manycore processor with on-chip learning,

    M. Davies, N. Srinivasa, T.-H. Lin, G. Chinya, Y . Cao, S. H. Choday, G. Dimou, P. Joshi, N. Imam, S. Jain et al. , “Loihi: A neuromorphic manycore processor with on-chip learning,” IEEE Micro, vol. 38, no. 1, pp. 82–99, 2018

    2018

  6. [6]

    Darwin3: a large-scale neuromorphic chip with a novel isa and on-chip learning,

    D. Ma, X. Jin, S. Sun, Y . Li, X. Wu, Y . Hu, F. Yang, H. Tang, X. Zhu, P. Lin et al. , “Darwin3: a large-scale neuromorphic chip with a novel isa and on-chip learning,” National Science Review , vol. 11, no. 5, p. nwae102, 2024

    work page 2024

  7. [7]

    Sparse coding by spiking neural networks: Convergence theory and computational results,

    P. T. P. Tang, T.-H. Lin, and M. Davies, “Sparse coding by spiking neural networks: Convergence theory and computational results,” 2017. [Online]. Available: https://arxiv.org/abs/1705.05475

    arXiv 2017

  8. [8]

    Programming spiking neural networks on intel’s loihi,

    C.-K. Lin, A. Wild, G. N. Chinya, Y . Cao, M. Davies, D. M. Lavery, and H. Wang, “Programming spiking neural networks on intel’s loihi,” Computer, vol. 51, pp. 52–61, 2018

    work page 2018

Show all 41 references
  1. [9]

    Attention is all you need,

    A. Vaswani, “Attention is all you need,” Advances in Neural Information Processing Systems, 2017

    2017

  2. [10]

    Con- version of continuous-valued deep networks to efficient event-driven networks for image classification,

    B. Rueckauer, I.-A. Lungu, Y . Hu, M. Pfeiffer, and S.-C. Liu, “Con- version of continuous-valued deep networks to efficient event-driven networks for image classification,” Frontiers in neuroscience , vol. 11, p. 682, 2017

    2017

  3. [11]

    Going deeper in spiking neural networks: Vgg and residual architectures,

    A. Sengupta, Y . Ye, R. Wang, C. Liu, and K. Roy, “Going deeper in spiking neural networks: Vgg and residual architectures,” Frontiers in neuroscience, vol. 13, p. 95, 2019

    2019

  4. [12]

    Spiking-yolo: spiking neural network for energy-efficient object detection,

    S. Kim, S. Park, B. Na, and S. Yoon, “Spiking-yolo: spiking neural network for energy-efficient object detection,” in Proceedings of the AAAI conference on artificial intelligence , vol. 34, 2020, pp. 11 270– 11 277

    2020

  5. [13]

    Spiking deep convolutional neural networks for energy-efficient object recognition,

    Y . Cao, Y . Chen, and D. Khosla, “Spiking deep convolutional neural networks for energy-efficient object recognition,” International Journal of Computer Vision , vol. 113, pp. 54–66, 2015

    2015

  6. [14]

    Fast- classifying, high-accuracy spiking deep networks through weight and threshold balancing,

    P. U. Diehl, D. Neil, J. Binas, M. Cook, S.-C. Liu, and M. Pfeiffer, “Fast- classifying, high-accuracy spiking deep networks through weight and threshold balancing,” in 2015 International joint conference on neural networks (IJCNN), 2015, pp. 1–8

    2015

  7. [15]

    Rmp-snn: Residual membrane potential neuron for enabling deeper high-accuracy and low-latency spiking neural network,

    B. Han, G. Srinivasan, and K. Roy, “Rmp-snn: Residual membrane potential neuron for enabling deeper high-accuracy and low-latency spiking neural network,” in Proceedings of the IEEE/CVF conference on computer vision and pattern recognition , 2020, pp. 13 558–13 567

    2020

  8. [16]

    Optimal conversion of conventional artificial neural networks to spiking neural networks,

    S. Deng and S. Gu, “Optimal conversion of conventional artificial neural networks to spiking neural networks,” arXiv preprint arXiv:2103.00476, 2021

    2021 arXiv

  9. [17]

    Error-aware conversion from ann to snn via post-training parameter calibration,

    Y . Li, S. Deng, X. Dong, and S. Gu, “Error-aware conversion from ann to snn via post-training parameter calibration,” International Journal of Computer Vision, pp. 1–24, 2024

    2024

  10. [18]

    Brain-inspired multi- layer perceptron with spiking neurons,

    W. Li, H. Chen, J. Guo, Z. Zhang, and Y . Wang, “Brain-inspired multi- layer perceptron with spiking neurons,” in 2022 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR) , 2022, pp. 773– 783

    2022

  11. [19]

    Fast-snn: fast spiking neural network by converting quantized ann,

    Y . Hu, Q. Zheng, X. Jiang, and G. Pan, “Fast-snn: fast spiking neural network by converting quantized ann,” IEEE Transactions on Pattern Analysis and Machine Intelligence , 2023

    2023

  12. [20]

    Spatio-temporal backpropa- gation for training high-performance spiking neural networks,

    Y . Wu, L. Deng, G. Li, J. Zhu, and L. Shi, “Spatio-temporal backpropa- gation for training high-performance spiking neural networks,” Frontiers in neuroscience, vol. 12, p. 331, 2018

    2018

  13. [21]

    Direct training for spiking neural networks: Faster, larger, better,

    Y . Wu, L. Deng, G. Li, J. Zhu, Y . Xie, and L. Shi, “Direct training for spiking neural networks: Faster, larger, better,” in Proceedings of the AAAI conference on artificial intelligence, vol. 33, 2019, pp. 1311–1318

    2019

  14. [22]

    Going deeper with directly-trained larger spiking neural networks,

    H. Zheng, Y . Wu, L. Deng, Y . Hu, and G. Li, “Going deeper with directly-trained larger spiking neural networks,” in Proceedings of the AAAI conference on artificial intelligence , vol. 35, 2021, pp. 11 062– 11 070

    2021

  15. [23]

    Multi-level firing with spiking ds-resnet: Enabling better and deeper directly-trained spiking neural networks,

    L. Feng, Q. Liu, H. Tang, D. Ma, and G. Pan, “Multi-level firing with spiking ds-resnet: Enabling better and deeper directly-trained spiking neural networks,” in Proceedings of the International Joint Conference on Artificial Intelligence , 2022, pp. 2471–2477

    2022

  16. [24]

    Towards memory-and time-efficient backpropagation for training spiking neural networks,

    Q. Meng, M. Xiao, S. Yan, Y . Wang, Z. Lin, and Z.-Q. Luo, “Towards memory-and time-efficient backpropagation for training spiking neural networks,” in Proceedings of the IEEE/CVF International Conference on Computer Vision , 2023, pp. 6166–6176

    2023

  17. [25]

    An efficient spiking neural network for recognizing gestures with a dvs camera on the loihi neuromorphic processor,

    R. Massa, A. Marchisio, M. Martina, and M. Shafique, “An efficient spiking neural network for recognizing gestures with a dvs camera on the loihi neuromorphic processor,” in 2020 International Joint Conference on Neural Networks (IJCNN) , 2020, pp. 1–9

    2020

  18. [26]

    In-hardware learning of multilayer spiking neural networks on a neuromorphic processor,

    A. Shrestha, H. Fang, D. P. Rider, Z. Mei, and Q. Qiu, “In-hardware learning of multilayer spiking neural networks on a neuromorphic processor,” in 2021 58th ACM/IEEE Design Automation Conference (DAC), 2021, pp. 367–372

    2021

  19. [27]

    The backpropagation algorithm implemented on spiking neuromorphic hard- ware,

    A. Renner, F. Sheldon, A. Zlotnik, L. Tao, and A. Sornborger, “The backpropagation algorithm implemented on spiking neuromorphic hard- ware,” Nature Communications, vol. 15, no. 1, p. 9691, 2024

    2024

  20. [28]

    A 28-nm convolutional neuromor- phic processor enabling online learning with spike-based retinas,

    C. Frenkel, J.-D. Legat, and D. Bol, “A 28-nm convolutional neuromor- phic processor enabling online learning with spike-based retinas,” in 2020 IEEE International Symposium on Circuits and Systems (ISCAS) , 2020, pp. 1–5

    2020

  21. [29]

    Fast and energy-efficient neuromorphic deep learning with first-spike times,

    J. G ¨oltz, L. Kriener, A. Baumbach, S. Billaudelle, O. Breitwieser, B. Cramer, D. Dold, A. F. Kungl, W. Senn, J. Schemmel et al. , “Fast and energy-efficient neuromorphic deep learning with first-spike times,” Nature machine intelligence , vol. 3, no. 9, pp. 823–835, 2021

    2021

  22. [30]

    hxtorch. snn: Machine-learning-inspired spiking neural network modeling on brainscales-2,

    P. Spilger, E. Arnold, L. Blessing, C. Mauch, C. Pehle, E. M ¨uller, and J. Schemmel, “hxtorch. snn: Machine-learning-inspired spiking neural network modeling on brainscales-2,” in Proceedings of the 2023 Annual Neuro-Inspired Computational Elements Conference , 2023, pp. 57–62

    2023

  23. [31]

    Efficient algorithms for accelerating spiking neural networks on mac array of spinnaker 2,

    J. Huang, F. Kelber, B. V ogginger, B. Wu, F. Kreutz, P. Gerhards, D. Scholz, K. Knobloch, and C. G. Mayr, “Efficient algorithms for accelerating spiking neural networks on mac array of spinnaker 2,” in 2023 IEEE 5th International Conference on Artificial Intelligence Circuits...

    2023

  24. [32]

    Quantization and training of neural networks for efficient integer-arithmetic-only inference,

    B. Jacob, S. Kligys, B. Chen, M. Zhu, M. Tang, A. Howard, H. Adam, and D. Kalenichenko, “Quantization and training of neural networks for efficient integer-arithmetic-only inference,” in Proceedings of the IEEE conference on computer vision and pattern recognition, 2018, pp. 2...

    2018

  25. [33]

    1.1 computing’s energy problem (and what we can do about it),

    M. Horowitz, “1.1 computing’s energy problem (and what we can do about it),” in 2014 IEEE international solid-state circuits conference digest of technical papers (ISSCC) , 2014, pp. 10–14

    2014

  26. [34]

    Spikeconverter: An efficient conversion framework zipping the gap between artificial neural networks and spiking neural networks,

    F. Liu, W. Zhao, Y . Chen, Z. Wang, and L. Jiang, “Spikeconverter: An efficient conversion framework zipping the gap between artificial neural networks and spiking neural networks,” in Proceedings of the AAAI Conference on Artificial Intelligence , vol. 36, 2022, pp. 1692–1701

    2022

  27. [35]

    Pytorch: An imperative style, high- performance deep learning library,

    A. Paszke, S. Gross, F. Massa, A. Lerer, J. Bradbury, G. Chanan, T. Killeen, Z. Lin, N. Gimelshein, L. Antiga, A. Desmaison, A. Kopf, E. Yang, Z. DeVito, M. Raison, A. Tejani, S. Chilamkurthy, B. Steiner, L. Fang, J. Bai, and S. Chintala, “Pytorch: An imperative style, high- p...

    2019

  28. [36]

    Learning multiple layers of features from tiny images,

    A. Krizhevsky, “Learning multiple layers of features from tiny images,” in Proceedings of the International Conference on Machine Learning , 2009

    2009

  29. [37]

    Imagenet: A large-scale hierarchical image database,

    J. Deng, W. Dong, R. Socher, L.-J. Li, K. Li, and L. Fei-Fei, “Imagenet: A large-scale hierarchical image database,” 2009 IEEE Conference on Computer Vision and Pattern Recognition (CVPR) , pp. 248–255, 2009

    2009

  30. [38]

    The pascal visual object classes homepage,

    M. Everingham, L. van Gool, C. Williams, J. Winn, A. Zisserman, Y . Aytar, A. Eslami, and A. Sorokin, “The pascal visual object classes homepage,” http://host.robots.ox.ac.uk/pascal/VOC/, 2012

    2012

  31. [39]

    You only look once: Unified, real-time object detection,

    J. Redmon, S. Divvala, R. Girshick, and A. Farhadi, “You only look once: Unified, real-time object detection,” in Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition (CVPR), 2016

    2016

  32. [40]

    Constructing deep spiking neural networks from artificial neural networks with knowledge distillation,

    Q. Xu, Y . Li, J. Shen, J. K. Liu, H. Tang, and G. Pan, “Constructing deep spiking neural networks from artificial neural networks with knowledge distillation,” in 2023 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR), 2023, pp. 7886–7895

    2023

  33. [41]

    Incorporating learnable membrane time constant to enhance learning of spiking neural networks,

    W. Fang, Z. Yu, Y . Chen, T. Masquelier, T. Huang, and Y . Tian, “Incorporating learnable membrane time constant to enhance learning of spiking neural networks,” in Proceedings of the IEEE/CVF international conference on computer vision , 2021, pp. 2661–2671

    2021

Pith tools

Reviewed August 15, 2026 · model on record in the stance chip above.